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Intel 41210 manual PCI 33 MHz Embedded Mode Topology, PCI 33 MHz Embedded Mode Routing Topology

Models: 41210

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8.6.5PCI 33 MHz Embedded Mode Topology

PCI-X Layout Guidelines

8.6.5PCI 33 MHz Embedded Mode Topology

Figure 22 and Table 14 provide routing details for a topology with an embedded PCI 33 MHz design.

Figure 22. PCI 33 MHz Embedded Mode Routing Topology

	EM1	EM3	EM5	EM7	EM9
	TL EM1	TL EM3	TL EM5	TL EM7	TL EM9
TL1	TL2	TL3	TL4		TL5
	TL EM2	TL EM4	TL EM6	TL EM8	TL EM10
	EM2	EM4	EM6	EM8	EM10
					B2723 -01

Table 14.	PCI 33 MHz Embedded Routing Recommendations

	Parameter	Routing Guideline for Lower AD Bus

	Reference Plane	Route over an unbroken ground plane

	Board Impedance	60 Ω +/- 15%

	Stripline Trace Spacing	12 mils, edge to edge

	Microstrip Trace Spacing	18 mils edge to edge

	Group Spacing	Spacing from other groups: 25 mils min, edge to edge

	Breakout	5 mils on 5 mils spacing. Maximum length of breakout region can be 500 mils.

	Trace Length 1 TL1: From
	41210 Bridge signal Ball to	5.0” max
	first junction

	Trace Length TL2 to TL5 -	0.5” min - 3.5” max
	between junctions	0.5” min - 3.5” max
	between junctions
	Trace Length TL_EM1 to
	TL_EM10 from junction to	2.0” min - 3.0” max
	embedded devices

	Length Matching	Clocks coming from the clock driver must be length matched to within 25 mils.
	Requirements
	Requirements

Intel® 41210 Serial to Parallel PCI Bridge Design Guide

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Intel 41210 manual PCI 33 MHz Embedded Mode Topology, PCI 33 MHz Embedded Mode Routing Topology, PCI-X Layout Guidelines

Contents

Intel 41210 Serial to Parallel PCI Bridge Design GuideIntel 41210 Serial to Parallel PCI Bridge Design Guide Contents ContentsIntroduction Contents FiguresSMBUs Address Configuration TablesRevision History ContentsContents This page intentionally left blankIntel 41210 Serial to Parallel PCI Bridge Design Guide 1.1 Terminology and Definitions About This DocumentTable 1. Terminology and Definitions Sheet 1 of Table 1. Terminology and Definitions Sheet 2 of About This DocumentIntel 41210 Serial to Parallel PCI Bridge Design Guide 2.2 PCI-X Interface Features 2.1 PCI Express Interface FeaturesIntroduction2 Introduction 2.3 Power Management2.4.1 SMBus for configuration register initialization 2.4 SMBus InterfaceConfiguration Figure 1. 41210 Bridge Microcontroller Block Diagram2.4.2 Microcontroller Connections to the 41210 Bridge Figure 2. 41210 Bridge Microcontroller ConnectionsIntelﬁ 41210 Bridge A Figure 3. 41210 Bridge Block Diagram2.5 JTAG 2.6 Related Documents2.7 Intel41210 Serial to Parallel PCI Bridge Applications Figure 4. Intel 41210 Bridge Adapter Card Block DiagramIntroduction Introduction This page intentionally left blankIntel 41210 Serial to Parallel PCI Bridge Design Guide Intel 41210 Serial to Parallel PCI Bridge Design Guide 3.1 Package SpecificationFigure 5. Top View - 41210 Bridge 567-Ball FCBGA Package Dimensions Package InformationIntel 41210 Serial to Parallel PCI Bridge Design Guide Package InformationB2711-01 B2712-01 Figure 7. Side View - 41210 Bridge 567-Ball FCBGA Package DimensionsPackage Information Intel 41210 Serial to Parallel PCI Bridge Design GuidePackage Information This page intentionally left blankIntel 41210 Serial to Parallel PCI Bridge Design Guide 4.1 41210 Bridge Decoupling Guidelines Power Plane LayoutB2714-01 Power Plane LayoutIntel 41210 Serial to Parallel PCI Bridge Design Guide Capacitor LegendIntel 41210 Serial to Parallel PCI Bridge Design Guide 4.2 Split Voltage PlanesTable 2. 41210 Bridge Decoupling Guidelines Power Plane LayoutCore Figure 10. 41210 Bridge Single-Layer Split Voltage PlanePower Plane Layout PCI Express5.1 ARST#,BRST# and PERST# Timing Requirements 41210 Bridge Reset and Power Timing Considerations55.2 VCC15 and VCC33 Voltage Requirements This page intentionally left blank 41210 Bridge Reset and Power Timing ConsiderationsIntel 41210 Serial to Parallel PCI Bridge Design Guide 6.1 General Routing Guidelines General Routing Guidelines6.2 Crosstalk Figure 11. Crosstalk Effects on Trace Distance and Height Figure 12. PCB Ground Layout Around Connectors6.3 EMI Considerations General Routing Guidelineshttp//emclab.umr.edu/pcbtlc 6.4 Power Distribution and Decoupling6.5 Trace Impedance 6.4.1 DecouplingZ11 Z12 Z21 Z22 6.5.1 Differential ImpedanceFigure 13. Cross Section of Differential Trace Figure 14. Two-by-two Differential Impedance Matrix7.1 Adapter Card Topology Board Layout GuidelinesAdapter Card Stack Up, Microstrip and Stripline Figure 15. Adapter Card Stackup Board Layout GuidelinesIntel 41210 Serial to Parallel PCI Bridge Design Guide 8.1 Interrupts PCI-X Layout GuidelinesTable 4. INTx Routing Table Table 5. Interrupt Binding for Devices Behind a Bridge 8.2 PCI Arbitration8.1.1 Interrupt Routing for Devices Behind a Bridge PCI-X Layout GuidelinesPCI-X Layout Guidelines 8.3 PCI General Layout Guidelines8.2.1 PCI Resistor Compensation Figure 16. PCI RCOMPPCI-X Layout Guidelines Table 6. PCI-X Signals8.3.1 PCI Pullup Resistors Not Required Table 7. PCI/PCI-X Frequency/Mode StrapsPCI-X Layout Guidelines 8.4 PCI Clock Layout GuidelinesPCI Device PCI Device PCI Device PCI Device PCI Device Figure 17. PCI Clock Distribution and Matching RequirementsPCI-X Layout Guidelines Intel 41210 BridgeParameter PCI-X Clock Layout Requirements SummaryPCI-X Layout Guidelines Intel 41210 Serial to Parallel PCI Bridge Design GuidePCI-X Slot Guidelines 8.5 PCI-X Topology Layout GuidelinesPCI-X Layout Guidelines PCI-X Layout Guidelines 8.6.1 Embedded PCI-X 133 MHzFigure 18. Embedded PCI-X 133 MHz Topology Embedded PCI-X 133 MHz Routing RecommendationsPCI-X Layout Guidelines 8.6.2 Embedded PCI-X 100 MHzFigure 19. Embedded PCI-X 100 MHz Topology Embedded PCI-X 100 MHz Routing RecommendationsPCI-X Layout Guidelines 8.6.3 PCI-X 66 MHz Embedded TopologyFigure 20. PCI-X 66 MHz Embedded Routing Topology PCI-X 66 MHz Embedded Routing RecommendationsPCI-X Layout Guidelines 8.6.4 PCI 66 MHz Embedded TopologyFigure 21. PCI 66 MHz Embedded Topology PCI 66 MHz Embedded TablePCI-X Layout Guidelines 8.6.5 PCI 33 MHz Embedded Mode TopologyFigure 22. PCI 33 MHz Embedded Mode Routing Topology PCI 33 MHz Embedded Routing RecommendationsPCI-X Layout Guidelines This page intentionally left blankIntel 41210 Serial to Parallel PCI Bridge Design Guide 9.1 General recommendations PCI Express LayoutAdapter Card Routing Recommendations Sheet 1 of 9.2 PCI-Express Layout Guidelines9.3 Adapter Card Layout Guidelines PCI Express LayoutPCI Express Layout Table 15. Adapter Card Routing Recommendations Sheet 2 ofIntel 41210 Serial to Parallel PCI Bridge Design Guide PCI Express Layout This page intentionally left blankIntel 41210 Serial to Parallel PCI Bridge Design Guide 10.1 41210 Bridge Analog Voltage Filters Circuit ImplementationsFigure 23. PCI Analog Voltage Filter Circuit 10.1.1 PCI Analog Voltage Filters10.1.2 PCI Express Analog Voltage Filter Circuit ImplementationsFigure 24. PCI Express Analog Voltage Filter Circuit 10.1.3 Bandgap Analog Voltage FilterCircuit Implementations Circuit Implementations Bandgap Analog Voltage Filter CircuitB2726 Circuit Implementations Figure 26. Reference and Compensation Circuit Implementations10.2.1 SM Bus Table 17. SMBUs Address ConfigurationCircuit Implementations Intel 41210 Serial to Parallel PCI Bridge Design Guide 41210 Bridge Customer ReferenceBoards 11.1 Board Stack-upTable 18. CRB Board Stackup 11.2 Material11.3 Impedance 41210 Bridge Customer Reference BoardsU1 Intelﬁ Bridge 11.4 Board OutlineFigure 27. Mechanical Outline of the 41210 Bridge 41210 Bridge Customer Reference Boards41210 Bridge Customer Reference Boards This page intentionally left blankIntel 41210 Serial to Parallel PCI Bridge Design Guide Table 19. PCI Express Interface Signals Design Guide ChecklistIntel 41210 Serial to Parallel PCI Bridge Design Guide Table 20. PCI/PCI-X Interface Signals Design Guide ChecklistIntel 41210 Serial to Parallel PCI Bridge Design Guide Design without secondary PCI/PCI Design Guide ChecklistTable 20. PCI/PCI-X Interface Signals Intel 41210 Serial to Parallel PCI Bridge Design GuideTo retry configuration accesses to the 41210, pull high to Table 21. Miscellaneous SignalsTable 22. SMBus Interface Signals Design Guide ChecklistIntel 41210 Serial to Parallel PCI Bridge Design Guide Table 23. Power and Ground SignalsDesign Guide Checklist power down or any other time during system operationDesign Guide Checklist Table 24. JTAG SignalsIntel 41210 Serial to Parallel PCI Bridge Design Guide