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Intel 41210 manual Design Guide Checklist, PCI/PCI-X Interface Signals

Models: 41210

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Design Guide Checklist

Design Guide Checklist

Table 20. PCI/PCI-X Interface Signals

	Signals	Recommendations	Reason/Impact

	X_AD[63:32]
	X_CBE[7:4]#
	X_DEVSEL#
	X_FRAME#
	X_IRDY#
	X_TRDY#
	X_STOP#		41210 Bridge has internal pullup
	X_PERR#		resistors on these signals.
	X_PERR#	No external pullup resistors required on system board.	X_AD[31:0] and X_CBE#[3:0]
	X_SERR#	No external pullup resistors required on system board.	X_AD[31:0] and X_CBE#[3:0]
	X_SERR#		signals do not require pullups
	X_REQ[5:0]#		signals do not require pullups
	X_REQ[5:0]#		according to the PCI Specification.
	X_GNT[5:0]#
	X_LOCK#
	X_PAR
	X_PAR64
	X_ACK64#
	X_REQ64#

		Only relevant when running in PCI-X Mode
		(X_PCIXCAP = 1).
		Determines the max PCI-X Mode 1 frequency for a
	A_133EN	particular segment (100 MHz or 133 MHz):	Sampled on the rising edge of
	A_133EN	0 = 100 MHz PCI-X max frequency	Sampled on the rising edge of
	B_133EN	0 = 100 MHz PCI-X max frequency	PERST#.
	B_133EN	1 = 133 MHz PCI-X max frequency	PERST#.
		1 = 133 MHz PCI-X max frequency
		Use an 8.2KΩ pullup resistor to VCC33. This resistor is
		located on the system board.

	A_INTA#,
	A_INTB#,
	A_INTC#,
	A_INTD#,	No pullup resistors required on these signals.	The 41210 Bridge has internal
	B_INTA#,	No pullup resistors required on these signals.	pullup resistors on these signals.
	B_INTA#,		pullup resistors on these signals.
	B_INTB#,
	B_INTC#,
	B_INTD#

60	Intel® 41210 Serial to Parallel PCI Bridge Design Guide

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Intel manual Design Guide Checklist, PCI/PCI-X Interface Signals, Intel 41210 Serial to Parallel PCI Bridge Design Guide

Contents

Design Guide Intel 41210 Serial to Parallel PCI BridgeIntel 41210 Serial to Parallel PCI Bridge Design Guide Contents ContentsIntroduction Figures ContentsTables Revision HistoryContents SMBUs Address ConfigurationThis page intentionally left blank ContentsIntel 41210 Serial to Parallel PCI Bridge Design Guide About This Document 1.1 Terminology and DefinitionsTable 1. Terminology and Definitions Sheet 1 of About This Document Table 1. Terminology and Definitions Sheet 2 ofIntel 41210 Serial to Parallel PCI Bridge Design Guide 2.1 PCI Express Interface Features 2.2 PCI-X Interface FeaturesIntroduction2 2.3 Power Management 2.4.1 SMBus for configuration register initialization2.4 SMBus Interface IntroductionFigure 1. 41210 Bridge Microcontroller Block Diagram 2.4.2 Microcontroller Connections to the 41210 BridgeFigure 2. 41210 Bridge Microcontroller Connections ConfigurationFigure 3. 41210 Bridge Block Diagram 2.5 JTAG2.6 Related Documents Intelﬁ 41210 Bridge AFigure 4. Intel 41210 Bridge Adapter Card Block Diagram 2.7 Intel41210 Serial to Parallel PCI Bridge ApplicationsIntroduction This page intentionally left blank IntroductionIntel 41210 Serial to Parallel PCI Bridge Design Guide 3.1 Package Specification Figure 5. Top View - 41210 Bridge 567-Ball FCBGA Package DimensionsPackage Information Intel 41210 Serial to Parallel PCI Bridge Design GuidePackage Information Intel 41210 Serial to Parallel PCI Bridge Design GuideB2711-01 Figure 7. Side View - 41210 Bridge 567-Ball FCBGA Package Dimensions Package InformationIntel 41210 Serial to Parallel PCI Bridge Design Guide B2712-01This page intentionally left blank Package InformationIntel 41210 Serial to Parallel PCI Bridge Design Guide Power Plane Layout 4.1 41210 Bridge Decoupling GuidelinesPower Plane Layout Intel 41210 Serial to Parallel PCI Bridge Design GuideCapacitor Legend B2714-014.2 Split Voltage Planes Table 2. 41210 Bridge Decoupling GuidelinesPower Plane Layout Intel 41210 Serial to Parallel PCI Bridge Design GuideFigure 10. 41210 Bridge Single-Layer Split Voltage Plane Power Plane LayoutPCI Express Core41210 Bridge Reset and Power Timing Considerations5 5.1 ARST#,BRST# and PERST# Timing Requirements5.2 VCC15 and VCC33 Voltage Requirements 41210 Bridge Reset and Power Timing Considerations This page intentionally left blankIntel 41210 Serial to Parallel PCI Bridge Design Guide General Routing Guidelines 6.1 General Routing Guidelines6.2 Crosstalk Figure 12. PCB Ground Layout Around Connectors 6.3 EMI ConsiderationsGeneral Routing Guidelines Figure 11. Crosstalk Effects on Trace Distance and Height6.4 Power Distribution and Decoupling 6.5 Trace Impedance6.4.1 Decoupling http//emclab.umr.edu/pcbtlc6.5.1 Differential Impedance Figure 13. Cross Section of Differential TraceFigure 14. Two-by-two Differential Impedance Matrix Z11 Z12 Z21 Z22Board Layout Guidelines 7.1 Adapter Card TopologyAdapter Card Stack Up, Microstrip and Stripline Board Layout Guidelines Figure 15. Adapter Card StackupIntel 41210 Serial to Parallel PCI Bridge Design Guide PCI-X Layout Guidelines 8.1 InterruptsTable 4. INTx Routing Table 8.2 PCI Arbitration 8.1.1 Interrupt Routing for Devices Behind a BridgePCI-X Layout Guidelines Table 5. Interrupt Binding for Devices Behind a Bridge8.3 PCI General Layout Guidelines 8.2.1 PCI Resistor CompensationFigure 16. PCI RCOMP PCI-X Layout GuidelinesTable 6. PCI-X Signals 8.3.1 PCI Pullup Resistors Not RequiredTable 7. PCI/PCI-X Frequency/Mode Straps PCI-X Layout Guidelines8.4 PCI Clock Layout Guidelines PCI-X Layout GuidelinesFigure 17. PCI Clock Distribution and Matching Requirements PCI-X Layout GuidelinesIntel 41210 Bridge PCI Device PCI Device PCI Device PCI Device PCI DevicePCI-X Clock Layout Requirements Summary PCI-X Layout GuidelinesIntel 41210 Serial to Parallel PCI Bridge Design Guide Parameter8.5 PCI-X Topology Layout Guidelines PCI-X Slot GuidelinesPCI-X Layout Guidelines 8.6.1 Embedded PCI-X 133 MHz Figure 18. Embedded PCI-X 133 MHz TopologyEmbedded PCI-X 133 MHz Routing Recommendations PCI-X Layout Guidelines8.6.2 Embedded PCI-X 100 MHz Figure 19. Embedded PCI-X 100 MHz TopologyEmbedded PCI-X 100 MHz Routing Recommendations PCI-X Layout Guidelines8.6.3 PCI-X 66 MHz Embedded Topology Figure 20. PCI-X 66 MHz Embedded Routing TopologyPCI-X 66 MHz Embedded Routing Recommendations PCI-X Layout Guidelines8.6.4 PCI 66 MHz Embedded Topology Figure 21. PCI 66 MHz Embedded TopologyPCI 66 MHz Embedded Table PCI-X Layout Guidelines8.6.5 PCI 33 MHz Embedded Mode Topology Figure 22. PCI 33 MHz Embedded Mode Routing TopologyPCI 33 MHz Embedded Routing Recommendations PCI-X Layout GuidelinesThis page intentionally left blank PCI-X Layout GuidelinesIntel 41210 Serial to Parallel PCI Bridge Design Guide PCI Express Layout 9.1 General recommendations9.2 PCI-Express Layout Guidelines 9.3 Adapter Card Layout GuidelinesPCI Express Layout Adapter Card Routing Recommendations Sheet 1 ofTable 15. Adapter Card Routing Recommendations Sheet 2 of PCI Express LayoutIntel 41210 Serial to Parallel PCI Bridge Design Guide This page intentionally left blank PCI Express LayoutIntel 41210 Serial to Parallel PCI Bridge Design Guide Circuit Implementations 10.1 41210 Bridge Analog Voltage Filters10.1.1 PCI Analog Voltage Filters 10.1.2 PCI Express Analog Voltage FilterCircuit Implementations Figure 23. PCI Analog Voltage Filter Circuit10.1.3 Bandgap Analog Voltage Filter Figure 24. PCI Express Analog Voltage Filter CircuitCircuit Implementations Bandgap Analog Voltage Filter Circuit Circuit ImplementationsB2726 Figure 26. Reference and Compensation Circuit Implementations Circuit ImplementationsTable 17. SMBUs Address Configuration 10.2.1 SM BusCircuit Implementations 41210 Bridge Customer Reference Boards11.1 Board Stack-up Intel 41210 Serial to Parallel PCI Bridge Design Guide11.2 Material 11.3 Impedance41210 Bridge Customer Reference Boards Table 18. CRB Board Stackup11.4 Board Outline Figure 27. Mechanical Outline of the 41210 Bridge41210 Bridge Customer Reference Boards U1 Intelﬁ BridgeThis page intentionally left blank 41210 Bridge Customer Reference BoardsIntel 41210 Serial to Parallel PCI Bridge Design Guide Design Guide Checklist Table 19. PCI Express Interface SignalsIntel 41210 Serial to Parallel PCI Bridge Design Guide Design Guide Checklist Table 20. PCI/PCI-X Interface SignalsIntel 41210 Serial to Parallel PCI Bridge Design Guide Design Guide Checklist Table 20. PCI/PCI-X Interface SignalsIntel 41210 Serial to Parallel PCI Bridge Design Guide Design without secondary PCI/PCITable 21. Miscellaneous Signals Table 22. SMBus Interface SignalsDesign Guide Checklist To retry configuration accesses to the 41210, pull high toTable 23. Power and Ground Signals Design Guide Checklistpower down or any other time during system operation Intel 41210 Serial to Parallel PCI Bridge Design GuideTable 24. JTAG Signals Design Guide ChecklistIntel 41210 Serial to Parallel PCI Bridge Design Guide