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Intel 41210 Embedded PCI-X 133 MHz Topology, Embedded PCI-X 133 MHz Routing Recommendations

Models: 41210

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8.6.1Embedded PCI-X 133 MHz

PCI-X Layout Guidelines

8.6.1Embedded PCI-X 133 MHz

This section lists the routing recommendations for PCI-X 133 MHz without a slot. Figure 18 shows the block diagram of this topology and Table 10 describes the routing recommendations.

Figure 18. Embedded PCI-X 133 MHz Topology

		EM1
		TL EM1
		TL1
		TL EM2
		EM2
			B2719 -01

Table 10.	Embedded PCI-X 133 MHz Routing Recommendations

	Parameter	Routing Guideline for Lower AD Bus

	Reference Plane	Route over an unbroken ground plane

	Board Impedance	60 Ω +/- 15%

	Stripline Trace Spacing	12 mils from edge to edge

	Microstrip Trace Spacing	18 mils, from edge to edge

	Break Out	5 mils on 5 mils spacing. Maximum length of breakout region can be 500 mils

	Group Spacing	Spacing from other groups: 25 mils min, edge to edge

	Trace Length 1 (TL1): From
	41210 Bridge signal Ball to	1.75” min - 4.0” max
	first junction

	Trace Length 3 junction of
	TL_EM1 and TL_EM2 to the	1.25” min - 3.25” max
	embedded device
	Length Matching	Clocks coming form the clock driver must be on the same layer and length
	Requirements:	matched to within 25 mils.

	Number of vias	3 vias max per path

Intel® 41210 Serial to Parallel PCI Bridge Design Guide

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Intel 41210 Embedded PCI-X 133 MHz Topology, Embedded PCI-X 133 MHz Routing Recommendations, PCI-X Layout Guidelines

Contents

Intel 41210 Serial to Parallel PCI Bridge Design GuideIntel 41210 Serial to Parallel PCI Bridge Design Guide Contents ContentsIntroduction Contents FiguresSMBUs Address Configuration TablesRevision History ContentsThis page intentionally left blank ContentsIntel 41210 Serial to Parallel PCI Bridge Design Guide About This Document 1.1 Terminology and DefinitionsTable 1. Terminology and Definitions Sheet 1 of About This Document Table 1. Terminology and Definitions Sheet 2 ofIntel 41210 Serial to Parallel PCI Bridge Design Guide 2.1 PCI Express Interface Features 2.2 PCI-X Interface FeaturesIntroduction2 Introduction 2.3 Power Management2.4.1 SMBus for configuration register initialization 2.4 SMBus InterfaceConfiguration Figure 1. 41210 Bridge Microcontroller Block Diagram2.4.2 Microcontroller Connections to the 41210 Bridge Figure 2. 41210 Bridge Microcontroller ConnectionsIntelﬁ 41210 Bridge A Figure 3. 41210 Bridge Block Diagram2.5 JTAG 2.6 Related DocumentsFigure 4. Intel 41210 Bridge Adapter Card Block Diagram 2.7 Intel41210 Serial to Parallel PCI Bridge ApplicationsIntroduction This page intentionally left blank IntroductionIntel 41210 Serial to Parallel PCI Bridge Design Guide Intel 41210 Serial to Parallel PCI Bridge Design Guide 3.1 Package SpecificationFigure 5. Top View - 41210 Bridge 567-Ball FCBGA Package Dimensions Package InformationPackage Information Intel 41210 Serial to Parallel PCI Bridge Design GuideB2711-01 B2712-01 Figure 7. Side View - 41210 Bridge 567-Ball FCBGA Package DimensionsPackage Information Intel 41210 Serial to Parallel PCI Bridge Design GuideThis page intentionally left blank Package InformationIntel 41210 Serial to Parallel PCI Bridge Design Guide 4.1 41210 Bridge Decoupling Guidelines Power Plane LayoutB2714-01 Power Plane LayoutIntel 41210 Serial to Parallel PCI Bridge Design Guide Capacitor LegendIntel 41210 Serial to Parallel PCI Bridge Design Guide 4.2 Split Voltage PlanesTable 2. 41210 Bridge Decoupling Guidelines Power Plane LayoutCore Figure 10. 41210 Bridge Single-Layer Split Voltage PlanePower Plane Layout PCI Express41210 Bridge Reset and Power Timing Considerations5 5.1 ARST#,BRST# and PERST# Timing Requirements5.2 VCC15 and VCC33 Voltage Requirements 41210 Bridge Reset and Power Timing Considerations This page intentionally left blankIntel 41210 Serial to Parallel PCI Bridge Design Guide General Routing Guidelines 6.1 General Routing Guidelines6.2 Crosstalk Figure 11. Crosstalk Effects on Trace Distance and Height Figure 12. PCB Ground Layout Around Connectors6.3 EMI Considerations General Routing Guidelineshttp//emclab.umr.edu/pcbtlc 6.4 Power Distribution and Decoupling6.5 Trace Impedance 6.4.1 DecouplingZ11 Z12 Z21 Z22 6.5.1 Differential ImpedanceFigure 13. Cross Section of Differential Trace Figure 14. Two-by-two Differential Impedance MatrixBoard Layout Guidelines 7.1 Adapter Card TopologyAdapter Card Stack Up, Microstrip and Stripline Board Layout Guidelines Figure 15. Adapter Card StackupIntel 41210 Serial to Parallel PCI Bridge Design Guide PCI-X Layout Guidelines 8.1 InterruptsTable 4. INTx Routing Table Table 5. Interrupt Binding for Devices Behind a Bridge 8.2 PCI Arbitration8.1.1 Interrupt Routing for Devices Behind a Bridge PCI-X Layout GuidelinesPCI-X Layout Guidelines 8.3 PCI General Layout Guidelines8.2.1 PCI Resistor Compensation Figure 16. PCI RCOMPPCI-X Layout Guidelines Table 6. PCI-X Signals8.3.1 PCI Pullup Resistors Not Required Table 7. PCI/PCI-X Frequency/Mode StrapsPCI-X Layout Guidelines 8.4 PCI Clock Layout GuidelinesPCI Device PCI Device PCI Device PCI Device PCI Device Figure 17. PCI Clock Distribution and Matching RequirementsPCI-X Layout Guidelines Intel 41210 BridgeParameter PCI-X Clock Layout Requirements SummaryPCI-X Layout Guidelines Intel 41210 Serial to Parallel PCI Bridge Design Guide8.5 PCI-X Topology Layout Guidelines PCI-X Slot GuidelinesPCI-X Layout Guidelines PCI-X Layout Guidelines 8.6.1 Embedded PCI-X 133 MHzFigure 18. Embedded PCI-X 133 MHz Topology Embedded PCI-X 133 MHz Routing RecommendationsPCI-X Layout Guidelines 8.6.2 Embedded PCI-X 100 MHzFigure 19. Embedded PCI-X 100 MHz Topology Embedded PCI-X 100 MHz Routing RecommendationsPCI-X Layout Guidelines 8.6.3 PCI-X 66 MHz Embedded TopologyFigure 20. PCI-X 66 MHz Embedded Routing Topology PCI-X 66 MHz Embedded Routing RecommendationsPCI-X Layout Guidelines 8.6.4 PCI 66 MHz Embedded TopologyFigure 21. PCI 66 MHz Embedded Topology PCI 66 MHz Embedded TablePCI-X Layout Guidelines 8.6.5 PCI 33 MHz Embedded Mode TopologyFigure 22. PCI 33 MHz Embedded Mode Routing Topology PCI 33 MHz Embedded Routing RecommendationsThis page intentionally left blank PCI-X Layout GuidelinesIntel 41210 Serial to Parallel PCI Bridge Design Guide 9.1 General recommendations PCI Express LayoutAdapter Card Routing Recommendations Sheet 1 of 9.2 PCI-Express Layout Guidelines9.3 Adapter Card Layout Guidelines PCI Express LayoutTable 15. Adapter Card Routing Recommendations Sheet 2 of PCI Express LayoutIntel 41210 Serial to Parallel PCI Bridge Design Guide This page intentionally left blank PCI Express LayoutIntel 41210 Serial to Parallel PCI Bridge Design Guide 10.1 41210 Bridge Analog Voltage Filters Circuit ImplementationsFigure 23. PCI Analog Voltage Filter Circuit 10.1.1 PCI Analog Voltage Filters10.1.2 PCI Express Analog Voltage Filter Circuit Implementations10.1.3 Bandgap Analog Voltage Filter Figure 24. PCI Express Analog Voltage Filter CircuitCircuit Implementations Bandgap Analog Voltage Filter Circuit Circuit ImplementationsB2726 Circuit Implementations Figure 26. Reference and Compensation Circuit ImplementationsTable 17. SMBUs Address Configuration 10.2.1 SM BusCircuit Implementations Intel 41210 Serial to Parallel PCI Bridge Design Guide 41210 Bridge Customer ReferenceBoards 11.1 Board Stack-upTable 18. CRB Board Stackup 11.2 Material11.3 Impedance 41210 Bridge Customer Reference BoardsU1 Intelﬁ Bridge 11.4 Board OutlineFigure 27. Mechanical Outline of the 41210 Bridge 41210 Bridge Customer Reference BoardsThis page intentionally left blank 41210 Bridge Customer Reference BoardsIntel 41210 Serial to Parallel PCI Bridge Design Guide Design Guide Checklist Table 19. PCI Express Interface SignalsIntel 41210 Serial to Parallel PCI Bridge Design Guide Design Guide Checklist Table 20. PCI/PCI-X Interface SignalsIntel 41210 Serial to Parallel PCI Bridge Design Guide Design without secondary PCI/PCI Design Guide ChecklistTable 20. PCI/PCI-X Interface Signals Intel 41210 Serial to Parallel PCI Bridge Design GuideTo retry configuration accesses to the 41210, pull high to Table 21. Miscellaneous SignalsTable 22. SMBus Interface Signals Design Guide ChecklistIntel 41210 Serial to Parallel PCI Bridge Design Guide Table 23. Power and Ground SignalsDesign Guide Checklist power down or any other time during system operationTable 24. JTAG Signals Design Guide ChecklistIntel 41210 Serial to Parallel PCI Bridge Design Guide