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Intel 41210 manual Board Layout Guidelines, Adapter Card Stackup

Models: 41210

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Board Layout Guidelines

NOTE: Each interface will set the trace spacing based on its signal integrity of differential impedance requirements. For the purposes of the building the transmission line models, it is assumed the artwork is very accurate and therefore a constant. Thus, all the variability in the trace spacing is the result of the tolerances of the trace width.

Figure 15. Adapter Card Stackup

Total Thickenss

Microstrip

Trace

Spacing

L2 (GND)

L4 (VCC)

Microstrip

Trace

Width

Microstrip Trace Thickness Solder Mask Thickness

Trace Height 1

Trace Height 2

Stripline Trace Thickness

Trace Height 3

Core Thickness

L5 (VCC)

L7 (GND)

Stripline

Trace

Spacing

Plane Thickness

Stripline

Trace

Width

B1436-01

30	Intel® 41210 Serial to Parallel PCI Bridge Design Guide

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Intel manual Board Layout Guidelines, Adapter Card Stackup, Intel 41210 Serial to Parallel PCI Bridge Design Guide

Contents

Design Guide Intel 41210 Serial to Parallel PCI BridgeIntel 41210 Serial to Parallel PCI Bridge Design Guide Contents ContentsIntroduction Figures ContentsContents TablesRevision History SMBUs Address ConfigurationThis page intentionally left blank ContentsIntel 41210 Serial to Parallel PCI Bridge Design Guide About This Document 1.1 Terminology and DefinitionsTable 1. Terminology and Definitions Sheet 1 of About This Document Table 1. Terminology and Definitions Sheet 2 ofIntel 41210 Serial to Parallel PCI Bridge Design Guide 2.1 PCI Express Interface Features 2.2 PCI-X Interface FeaturesIntroduction2 2.4 SMBus Interface 2.3 Power Management2.4.1 SMBus for configuration register initialization IntroductionFigure 2. 41210 Bridge Microcontroller Connections Figure 1. 41210 Bridge Microcontroller Block Diagram2.4.2 Microcontroller Connections to the 41210 Bridge Configuration2.6 Related Documents Figure 3. 41210 Bridge Block Diagram2.5 JTAG Intelﬁ 41210 Bridge AFigure 4. Intel 41210 Bridge Adapter Card Block Diagram 2.7 Intel41210 Serial to Parallel PCI Bridge ApplicationsIntroduction This page intentionally left blank IntroductionIntel 41210 Serial to Parallel PCI Bridge Design Guide Package Information 3.1 Package SpecificationFigure 5. Top View - 41210 Bridge 567-Ball FCBGA Package Dimensions Intel 41210 Serial to Parallel PCI Bridge Design GuidePackage Information Intel 41210 Serial to Parallel PCI Bridge Design GuideB2711-01 Intel 41210 Serial to Parallel PCI Bridge Design Guide Figure 7. Side View - 41210 Bridge 567-Ball FCBGA Package DimensionsPackage Information B2712-01This page intentionally left blank Package InformationIntel 41210 Serial to Parallel PCI Bridge Design Guide Power Plane Layout 4.1 41210 Bridge Decoupling GuidelinesCapacitor Legend Power Plane LayoutIntel 41210 Serial to Parallel PCI Bridge Design Guide B2714-01Power Plane Layout 4.2 Split Voltage PlanesTable 2. 41210 Bridge Decoupling Guidelines Intel 41210 Serial to Parallel PCI Bridge Design GuidePCI Express Figure 10. 41210 Bridge Single-Layer Split Voltage PlanePower Plane Layout Core41210 Bridge Reset and Power Timing Considerations5 5.1 ARST#,BRST# and PERST# Timing Requirements5.2 VCC15 and VCC33 Voltage Requirements 41210 Bridge Reset and Power Timing Considerations This page intentionally left blankIntel 41210 Serial to Parallel PCI Bridge Design Guide General Routing Guidelines 6.1 General Routing Guidelines6.2 Crosstalk General Routing Guidelines Figure 12. PCB Ground Layout Around Connectors6.3 EMI Considerations Figure 11. Crosstalk Effects on Trace Distance and Height6.4.1 Decoupling 6.4 Power Distribution and Decoupling6.5 Trace Impedance http//emclab.umr.edu/pcbtlcFigure 14. Two-by-two Differential Impedance Matrix 6.5.1 Differential ImpedanceFigure 13. Cross Section of Differential Trace Z11 Z12 Z21 Z22Board Layout Guidelines 7.1 Adapter Card TopologyAdapter Card Stack Up, Microstrip and Stripline Board Layout Guidelines Figure 15. Adapter Card StackupIntel 41210 Serial to Parallel PCI Bridge Design Guide PCI-X Layout Guidelines 8.1 InterruptsTable 4. INTx Routing Table PCI-X Layout Guidelines 8.2 PCI Arbitration8.1.1 Interrupt Routing for Devices Behind a Bridge Table 5. Interrupt Binding for Devices Behind a BridgeFigure 16. PCI RCOMP 8.3 PCI General Layout Guidelines8.2.1 PCI Resistor Compensation PCI-X Layout GuidelinesTable 7. PCI/PCI-X Frequency/Mode Straps Table 6. PCI-X Signals8.3.1 PCI Pullup Resistors Not Required PCI-X Layout Guidelines8.4 PCI Clock Layout Guidelines PCI-X Layout GuidelinesIntel 41210 Bridge Figure 17. PCI Clock Distribution and Matching RequirementsPCI-X Layout Guidelines PCI Device PCI Device PCI Device PCI Device PCI DeviceIntel 41210 Serial to Parallel PCI Bridge Design Guide PCI-X Clock Layout Requirements SummaryPCI-X Layout Guidelines Parameter8.5 PCI-X Topology Layout Guidelines PCI-X Slot GuidelinesPCI-X Layout Guidelines Embedded PCI-X 133 MHz Routing Recommendations 8.6.1 Embedded PCI-X 133 MHzFigure 18. Embedded PCI-X 133 MHz Topology PCI-X Layout GuidelinesEmbedded PCI-X 100 MHz Routing Recommendations 8.6.2 Embedded PCI-X 100 MHzFigure 19. Embedded PCI-X 100 MHz Topology PCI-X Layout GuidelinesPCI-X 66 MHz Embedded Routing Recommendations 8.6.3 PCI-X 66 MHz Embedded TopologyFigure 20. PCI-X 66 MHz Embedded Routing Topology PCI-X Layout GuidelinesPCI 66 MHz Embedded Table 8.6.4 PCI 66 MHz Embedded TopologyFigure 21. PCI 66 MHz Embedded Topology PCI-X Layout GuidelinesPCI 33 MHz Embedded Routing Recommendations 8.6.5 PCI 33 MHz Embedded Mode TopologyFigure 22. PCI 33 MHz Embedded Mode Routing Topology PCI-X Layout GuidelinesThis page intentionally left blank PCI-X Layout GuidelinesIntel 41210 Serial to Parallel PCI Bridge Design Guide PCI Express Layout 9.1 General recommendationsPCI Express Layout 9.2 PCI-Express Layout Guidelines9.3 Adapter Card Layout Guidelines Adapter Card Routing Recommendations Sheet 1 ofTable 15. Adapter Card Routing Recommendations Sheet 2 of PCI Express LayoutIntel 41210 Serial to Parallel PCI Bridge Design Guide This page intentionally left blank PCI Express LayoutIntel 41210 Serial to Parallel PCI Bridge Design Guide Circuit Implementations 10.1 41210 Bridge Analog Voltage FiltersCircuit Implementations 10.1.1 PCI Analog Voltage Filters10.1.2 PCI Express Analog Voltage Filter Figure 23. PCI Analog Voltage Filter Circuit10.1.3 Bandgap Analog Voltage Filter Figure 24. PCI Express Analog Voltage Filter CircuitCircuit Implementations Bandgap Analog Voltage Filter Circuit Circuit ImplementationsB2726 Figure 26. Reference and Compensation Circuit Implementations Circuit ImplementationsTable 17. SMBUs Address Configuration 10.2.1 SM BusCircuit Implementations 11.1 Board Stack-up 41210 Bridge Customer ReferenceBoards Intel 41210 Serial to Parallel PCI Bridge Design Guide41210 Bridge Customer Reference Boards 11.2 Material11.3 Impedance Table 18. CRB Board Stackup41210 Bridge Customer Reference Boards 11.4 Board OutlineFigure 27. Mechanical Outline of the 41210 Bridge U1 Intelﬁ BridgeThis page intentionally left blank 41210 Bridge Customer Reference BoardsIntel 41210 Serial to Parallel PCI Bridge Design Guide Design Guide Checklist Table 19. PCI Express Interface SignalsIntel 41210 Serial to Parallel PCI Bridge Design Guide Design Guide Checklist Table 20. PCI/PCI-X Interface SignalsIntel 41210 Serial to Parallel PCI Bridge Design Guide Intel 41210 Serial to Parallel PCI Bridge Design Guide Design Guide ChecklistTable 20. PCI/PCI-X Interface Signals Design without secondary PCI/PCIDesign Guide Checklist Table 21. Miscellaneous SignalsTable 22. SMBus Interface Signals To retry configuration accesses to the 41210, pull high topower down or any other time during system operation Table 23. Power and Ground SignalsDesign Guide Checklist Intel 41210 Serial to Parallel PCI Bridge Design GuideTable 24. JTAG Signals Design Guide ChecklistIntel 41210 Serial to Parallel PCI Bridge Design Guide