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Intel 41210 manual Introduction2, PCI Express Interface Features, PCI-X Interface Features

Models: 41210

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Introduction2

Introduction2

The Intel®41210 Serial to Parallel PCI Bridge integrates two PCI Express-to-PCI bridges. Each bridge follows the PCI-to-PCI Bridge programming model. The PCI Express port is compliant to the PCI Express Specification, Revision 1.0. The two PCI bus interfaces are fully compliant to the PCI Local Bus Specification, Revision 2.3.

2.1PCI Express Interface Features

•PCI Express Specification, Revision 1.0b compliant.

•Support for single x8, single x4 or single x1 PCI Express operation.

•64-bit addressing support.

•32-bit CRC (cyclic redundancy checking) covering all transmitted data packets.

•16-bit CRC on all link message information.

•Raw bit-rate on the data pins of 2.5 Gbit/s, resulting in a raw bandwidth per pin of 250 MB/s.

•Maximum realized bandwidth on PCI Express interface is 2 GB/s (in x8 mode) in each direction simultaneously, for an aggregate of 4 GB/s.

2.2PCI-X Interface Features

•PCI Local Bus Specification, Revision 2.3 compliant.

•PCI-to-PCI Bridge Specification, Revision 1.1 compliant.

•PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0a compliant.

•64-bit 66 MHz, 3.3 V, NOT 5 V tolerant.

•On Die Termination (ODT) with 8.2KΩ pull-up to 3.3V for PCI signals.

•Six external REQ/GNT Pairs for internal arbiter on segment A and B respectively.

•Programmable bus parking on either the last agent or always on Lanai.

•2-level programmable round-robin internal arbiter with Multi-Transaction Timer (MTT)

•External PCI clock-feed support for asynchronous primary and secondary domain operation.

•64-bit addressing for upstream and downstream transactions

•Downstream LOCK# support.

•No upstream LOCK# support.

•PCI fast Back-to-Back capable as target.

•Up to four active and four pending upstream memory read transactions

•Up to two downstream delayed (memory read, I/O read/write and configuration read/write) transaction.

Intel® 41210 Serial to Parallel PCI Bridge Design Guide

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Intel 41210 manual Introduction2, PCI Express Interface Features, PCI-X Interface Features

Contents

Intel 41210 Serial to Parallel PCI Bridge Design GuideIntel 41210 Serial to Parallel PCI Bridge Design Guide Contents ContentsIntroduction Contents FiguresRevision History TablesContents SMBUs Address ConfigurationThis page intentionally left blank ContentsIntel 41210 Serial to Parallel PCI Bridge Design Guide About This Document 1.1 Terminology and DefinitionsTable 1. Terminology and Definitions Sheet 1 of About This Document Table 1. Terminology and Definitions Sheet 2 ofIntel 41210 Serial to Parallel PCI Bridge Design Guide 2.1 PCI Express Interface Features 2.2 PCI-X Interface FeaturesIntroduction2 2.4.1 SMBus for configuration register initialization 2.3 Power Management2.4 SMBus Interface Introduction2.4.2 Microcontroller Connections to the 41210 Bridge Figure 1. 41210 Bridge Microcontroller Block DiagramFigure 2. 41210 Bridge Microcontroller Connections Configuration2.5 JTAG Figure 3. 41210 Bridge Block Diagram2.6 Related Documents Intelﬁ 41210 Bridge AFigure 4. Intel 41210 Bridge Adapter Card Block Diagram 2.7 Intel41210 Serial to Parallel PCI Bridge ApplicationsIntroduction This page intentionally left blank IntroductionIntel 41210 Serial to Parallel PCI Bridge Design Guide Figure 5. Top View - 41210 Bridge 567-Ball FCBGA Package Dimensions 3.1 Package SpecificationPackage Information Intel 41210 Serial to Parallel PCI Bridge Design GuidePackage Information Intel 41210 Serial to Parallel PCI Bridge Design GuideB2711-01 Package Information Figure 7. Side View - 41210 Bridge 567-Ball FCBGA Package DimensionsIntel 41210 Serial to Parallel PCI Bridge Design Guide B2712-01This page intentionally left blank Package InformationIntel 41210 Serial to Parallel PCI Bridge Design Guide 4.1 41210 Bridge Decoupling Guidelines Power Plane LayoutIntel 41210 Serial to Parallel PCI Bridge Design Guide Power Plane LayoutCapacitor Legend B2714-01Table 2. 41210 Bridge Decoupling Guidelines 4.2 Split Voltage PlanesPower Plane Layout Intel 41210 Serial to Parallel PCI Bridge Design GuidePower Plane Layout Figure 10. 41210 Bridge Single-Layer Split Voltage PlanePCI Express Core41210 Bridge Reset and Power Timing Considerations5 5.1 ARST#,BRST# and PERST# Timing Requirements5.2 VCC15 and VCC33 Voltage Requirements 41210 Bridge Reset and Power Timing Considerations This page intentionally left blankIntel 41210 Serial to Parallel PCI Bridge Design Guide General Routing Guidelines 6.1 General Routing Guidelines6.2 Crosstalk 6.3 EMI Considerations Figure 12. PCB Ground Layout Around ConnectorsGeneral Routing Guidelines Figure 11. Crosstalk Effects on Trace Distance and Height6.5 Trace Impedance 6.4 Power Distribution and Decoupling6.4.1 Decoupling http//emclab.umr.edu/pcbtlcFigure 13. Cross Section of Differential Trace 6.5.1 Differential ImpedanceFigure 14. Two-by-two Differential Impedance Matrix Z11 Z12 Z21 Z22Board Layout Guidelines 7.1 Adapter Card TopologyAdapter Card Stack Up, Microstrip and Stripline Board Layout Guidelines Figure 15. Adapter Card StackupIntel 41210 Serial to Parallel PCI Bridge Design Guide PCI-X Layout Guidelines 8.1 InterruptsTable 4. INTx Routing Table 8.1.1 Interrupt Routing for Devices Behind a Bridge 8.2 PCI ArbitrationPCI-X Layout Guidelines Table 5. Interrupt Binding for Devices Behind a Bridge8.2.1 PCI Resistor Compensation 8.3 PCI General Layout GuidelinesFigure 16. PCI RCOMP PCI-X Layout Guidelines8.3.1 PCI Pullup Resistors Not Required Table 6. PCI-X SignalsTable 7. PCI/PCI-X Frequency/Mode Straps PCI-X Layout GuidelinesPCI-X Layout Guidelines 8.4 PCI Clock Layout GuidelinesPCI-X Layout Guidelines Figure 17. PCI Clock Distribution and Matching RequirementsIntel 41210 Bridge PCI Device PCI Device PCI Device PCI Device PCI DevicePCI-X Layout Guidelines PCI-X Clock Layout Requirements SummaryIntel 41210 Serial to Parallel PCI Bridge Design Guide Parameter8.5 PCI-X Topology Layout Guidelines PCI-X Slot GuidelinesPCI-X Layout Guidelines Figure 18. Embedded PCI-X 133 MHz Topology 8.6.1 Embedded PCI-X 133 MHzEmbedded PCI-X 133 MHz Routing Recommendations PCI-X Layout GuidelinesFigure 19. Embedded PCI-X 100 MHz Topology 8.6.2 Embedded PCI-X 100 MHzEmbedded PCI-X 100 MHz Routing Recommendations PCI-X Layout GuidelinesFigure 20. PCI-X 66 MHz Embedded Routing Topology 8.6.3 PCI-X 66 MHz Embedded TopologyPCI-X 66 MHz Embedded Routing Recommendations PCI-X Layout GuidelinesFigure 21. PCI 66 MHz Embedded Topology 8.6.4 PCI 66 MHz Embedded TopologyPCI 66 MHz Embedded Table PCI-X Layout GuidelinesFigure 22. PCI 33 MHz Embedded Mode Routing Topology 8.6.5 PCI 33 MHz Embedded Mode TopologyPCI 33 MHz Embedded Routing Recommendations PCI-X Layout GuidelinesThis page intentionally left blank PCI-X Layout GuidelinesIntel 41210 Serial to Parallel PCI Bridge Design Guide 9.1 General recommendations PCI Express Layout9.3 Adapter Card Layout Guidelines 9.2 PCI-Express Layout GuidelinesPCI Express Layout Adapter Card Routing Recommendations Sheet 1 ofTable 15. Adapter Card Routing Recommendations Sheet 2 of PCI Express LayoutIntel 41210 Serial to Parallel PCI Bridge Design Guide This page intentionally left blank PCI Express LayoutIntel 41210 Serial to Parallel PCI Bridge Design Guide 10.1 41210 Bridge Analog Voltage Filters Circuit Implementations10.1.2 PCI Express Analog Voltage Filter 10.1.1 PCI Analog Voltage FiltersCircuit Implementations Figure 23. PCI Analog Voltage Filter Circuit10.1.3 Bandgap Analog Voltage Filter Figure 24. PCI Express Analog Voltage Filter CircuitCircuit Implementations Bandgap Analog Voltage Filter Circuit Circuit ImplementationsB2726 Circuit Implementations Figure 26. Reference and Compensation Circuit ImplementationsTable 17. SMBUs Address Configuration 10.2.1 SM BusCircuit Implementations Boards 41210 Bridge Customer Reference11.1 Board Stack-up Intel 41210 Serial to Parallel PCI Bridge Design Guide11.3 Impedance 11.2 Material41210 Bridge Customer Reference Boards Table 18. CRB Board StackupFigure 27. Mechanical Outline of the 41210 Bridge 11.4 Board Outline41210 Bridge Customer Reference Boards U1 Intelﬁ BridgeThis page intentionally left blank 41210 Bridge Customer Reference BoardsIntel 41210 Serial to Parallel PCI Bridge Design Guide Design Guide Checklist Table 19. PCI Express Interface SignalsIntel 41210 Serial to Parallel PCI Bridge Design Guide Design Guide Checklist Table 20. PCI/PCI-X Interface SignalsIntel 41210 Serial to Parallel PCI Bridge Design Guide Table 20. PCI/PCI-X Interface Signals Design Guide ChecklistIntel 41210 Serial to Parallel PCI Bridge Design Guide Design without secondary PCI/PCITable 22. SMBus Interface Signals Table 21. Miscellaneous SignalsDesign Guide Checklist To retry configuration accesses to the 41210, pull high toDesign Guide Checklist Table 23. Power and Ground Signalspower down or any other time during system operation Intel 41210 Serial to Parallel PCI Bridge Design GuideTable 24. JTAG Signals Design Guide ChecklistIntel 41210 Serial to Parallel PCI Bridge Design Guide