Introduction2, PCI Express Interface Features | Intel 41210 guide

Introduction2

The Intel®41210 Serial to Parallel PCI Bridge integrates two PCI Express-to-PCI bridges. Each bridge follows the PCI-to-PCI Bridge programming model. The PCI Express port is compliant to the PCI Express Specification, Revision 1.0. The two PCI bus interfaces are fully compliant to the PCI Local Bus Specification, Revision 2.3.

2.1PCI Express Interface Features

•PCI Express Specification, Revision 1.0b compliant.

•Support for single x8, single x4 or single x1 PCI Express operation.

•64-bit addressing support.

•32-bit CRC (cyclic redundancy checking) covering all transmitted data packets.

•16-bit CRC on all link message information.

•Raw bit-rate on the data pins of 2.5 Gbit/s, resulting in a raw bandwidth per pin of 250 MB/s.

•Maximum realized bandwidth on PCI Express interface is 2 GB/s (in x8 mode) in each direction simultaneously, for an aggregate of 4 GB/s.

2.2PCI-X Interface Features

•PCI Local Bus Specification, Revision 2.3 compliant.

•PCI-to-PCI Bridge Specification, Revision 1.1 compliant.

•PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0a compliant.

•64-bit 66 MHz, 3.3 V, NOT 5 V tolerant.

•On Die Termination (ODT) with 8.2KΩ pull-up to 3.3V for PCI signals.

•Six external REQ/GNT Pairs for internal arbiter on segment A and B respectively.

•Programmable bus parking on either the last agent or always on Lanai.

•2-level programmable round-robin internal arbiter with Multi-Transaction Timer (MTT)

•External PCI clock-feed support for asynchronous primary and secondary domain operation.

•64-bit addressing for upstream and downstream transactions

•Downstream LOCK# support.

•No upstream LOCK# support.

•PCI fast Back-to-Back capable as target.

•Up to four active and four pending upstream memory read transactions

•Up to two downstream delayed (memory read, I/O read/write and configuration read/write) transaction.

Intel® 41210 Serial to Parallel PCI Bridge Design Guide

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Intel 41210 manual Introduction2, PCI Express Interface Features, PCI-X Interface Features

Contents

Design Guide Intel 41210 Serial to Parallel PCI Bridge Intel 41210 Serial to Parallel PCI Bridge Design Guide Contents Figures Tables Revision HistoryDescription This page intentionally left blank Terminology and Definitions About This DocumentTerminology and Definitions Sheet 1 Term Definition Terminology and Definitions Sheet 2 About This Document PCI Express Interface Features PCI-X Interface FeaturesIntroduction2 SMBus for configuration register initialization Power ManagementSMBus Interface Introduction Microcontroller Connections to the 41210 Bridge Bridge Microcontroller Block Diagram Related Documents Jtag Intel41210 Serial to Parallel PCI Bridge Applications Intel 41210 Bridge Adapter Card Block Diagram This page intentionally left blank Package Information Package Specification Package Information Bottom View 41210 Bridge 567-Ball Fcbga Package Dimensions Side View 41210 Bridge 567-Ball Fcbga Package Dimensions This page intentionally left blank 41210 Bridge Decoupling Guidelines Power Plane Layout Power Plane Layout Bridge Decoupling Guidelines Split Voltage Planes PCI Bridge Reset and Power Timing Considerations5 ARST#,BRST# and PERST# Timing RequirementsVCC15 and VCC33 Voltage Requirements Bridge Reset and Power Timing Considerations General Routing Guidelines General Routing GuidelinesCrosstalk General Routing Guidelines EMI Considerations Power Distribution and Decoupling Trace ImpedanceDecoupling Cross Section of Differential Trace Differential Impedance Board Layout Guidelines Adapter Card TopologyAdapter Card Stack Up, Microstrip and Stripline Adapter Card Stackup Board Layout Guidelines PCI-X Layout Guidelines InterruptsINTx Routing Table Interrupt Routing for Devices Behind a Bridge PCI ArbitrationPCI-X Layout Guidelines Interrupt Binding for Devices Behind a Bridge PCI Resistor Compensation PCI General Layout Guidelines PCI-X Signals PCI Pullup Resistors Not RequiredPCI/PCI-X Frequency/Mode Straps BCBE#74, BDEVSEL#, BFRAME#, BINTA#, BINTB#, BINTC#, BINTD# PCI Clock Layout Guidelines PCI Clock Distribution and Matching Requirements Parameter Routing Guidelines PCI-X Clock Layout Requirements Summary PCI-X Slot Guidelines PCI-X Topology Layout Guidelines Embedded PCI-X 133 MHz Embedded PCI-X 133 MHz Routing RecommendationsParameter Routing Guideline for Lower AD Bus Embedded PCI-X 100 MHz Routing Recommendations Embedded PCI-X 100 MHz PCI-X 66 MHz Embedded Routing Recommendations PCI-X 66 MHz Embedded Topology PCI 66 MHz Embedded Table PCI 66 MHz Embedded Topology PCI 33 MHz Embedded Routing Recommendations PCI 33 MHz Embedded Mode Topology This page intentionally left blank General recommendations PCI Express Layout Adapter Card Layout Guidelines PCI-Express Layout GuidelinesPCI Express Layout Adapter Card Routing Recommendations Sheet 1 Adapter Card Routing Recommendations Sheet 2 This page intentionally left blank Config Circuit Implementations10.1 41210 Bridge Analog Voltage Filters PCI Analog Voltage Filters PCI Express Analog Voltage FilterCircuit Implementations Bandgap Analog Voltage Filter VccapeVssape Bandgap Analog Voltage Filter Circuit VccbgpeVSS Vssbgpe PERCOMP0 PERCOMP1 Rcomp Reference and Compensation Circuit Implementations SMBUs Address Configuration SM BusBit Value Board Stack-up Bridge Customer Reference Boards Material Layer Type Thickness Copper WeightImpedance Bridge Customer Reference Boards Mechanical Outline of the 41210 Bridge Board Outline This page intentionally left blank PCI Express Interface Signals Design Guide ChecklistSignals Recommendations Reason/Impact PERCOMP10 PCI/PCI-X Interface Signals Design Guide Checklist BM66EN PERST# AM66ENApcixcap Bpcixcap Miscellaneous Signals SMBus Interface SignalsSignals Signal Recommendations Reason/Impact Power and Ground SignalsVCC15 VCC33 Jtag Signals