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Intel Power Plane Layout, Intel 41210 Serial to Parallel PCI Bridge Design Guide, B2714-01

Models: 41210

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Power Plane Layout

Figure 9. Decoupling Placement for PCI/PCI-X 1.5V and 3.3V Voltage Planes

Capacitor Legend

0603-0.1 F

0603-1 F

1206-10 F

B2714-01

20	Intel® 41210 Serial to Parallel PCI Bridge Design Guide

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Intel manual Power Plane Layout, Intel 41210 Serial to Parallel PCI Bridge Design Guide, Capacitor Legend, B2714-01

Contents

Design Guide Intel 41210 Serial to Parallel PCI BridgeIntel 41210 Serial to Parallel PCI Bridge Design Guide Introduction ContentsContents Figures ContentsTables Revision HistoryContents SMBUs Address ConfigurationIntel 41210 Serial to Parallel PCI Bridge Design Guide This page intentionally left blankContents Table 1. Terminology and Definitions Sheet 1 of About This Document1.1 Terminology and Definitions Intel 41210 Serial to Parallel PCI Bridge Design Guide About This DocumentTable 1. Terminology and Definitions Sheet 2 of Introduction2 2.1 PCI Express Interface Features2.2 PCI-X Interface Features 2.3 Power Management 2.4.1 SMBus for configuration register initialization2.4 SMBus Interface IntroductionFigure 1. 41210 Bridge Microcontroller Block Diagram 2.4.2 Microcontroller Connections to the 41210 BridgeFigure 2. 41210 Bridge Microcontroller Connections ConfigurationFigure 3. 41210 Bridge Block Diagram 2.5 JTAG2.6 Related Documents Intelﬁ 41210 Bridge AIntroduction Figure 4. Intel 41210 Bridge Adapter Card Block Diagram2.7 Intel41210 Serial to Parallel PCI Bridge Applications Intel 41210 Serial to Parallel PCI Bridge Design Guide This page intentionally left blankIntroduction 3.1 Package Specification Figure 5. Top View - 41210 Bridge 567-Ball FCBGA Package DimensionsPackage Information Intel 41210 Serial to Parallel PCI Bridge Design GuideB2711-01 Package InformationIntel 41210 Serial to Parallel PCI Bridge Design Guide Figure 7. Side View - 41210 Bridge 567-Ball FCBGA Package Dimensions Package InformationIntel 41210 Serial to Parallel PCI Bridge Design Guide B2712-01Intel 41210 Serial to Parallel PCI Bridge Design Guide This page intentionally left blankPackage Information Power Plane Layout 4.1 41210 Bridge Decoupling GuidelinesPower Plane Layout Intel 41210 Serial to Parallel PCI Bridge Design GuideCapacitor Legend B2714-014.2 Split Voltage Planes Table 2. 41210 Bridge Decoupling GuidelinesPower Plane Layout Intel 41210 Serial to Parallel PCI Bridge Design GuideFigure 10. 41210 Bridge Single-Layer Split Voltage Plane Power Plane LayoutPCI Express Core5.2 VCC15 and VCC33 Voltage Requirements 41210 Bridge Reset and Power Timing Considerations55.1 ARST#,BRST# and PERST# Timing Requirements Intel 41210 Serial to Parallel PCI Bridge Design Guide 41210 Bridge Reset and Power Timing ConsiderationsThis page intentionally left blank 6.2 Crosstalk General Routing Guidelines6.1 General Routing Guidelines Figure 12. PCB Ground Layout Around Connectors 6.3 EMI ConsiderationsGeneral Routing Guidelines Figure 11. Crosstalk Effects on Trace Distance and Height6.4 Power Distribution and Decoupling 6.5 Trace Impedance6.4.1 Decoupling http//emclab.umr.edu/pcbtlc6.5.1 Differential Impedance Figure 13. Cross Section of Differential TraceFigure 14. Two-by-two Differential Impedance Matrix Z11 Z12 Z21 Z22Adapter Card Stack Up, Microstrip and Stripline Board Layout Guidelines7.1 Adapter Card Topology Intel 41210 Serial to Parallel PCI Bridge Design Guide Board Layout GuidelinesFigure 15. Adapter Card Stackup Table 4. INTx Routing Table PCI-X Layout Guidelines8.1 Interrupts 8.2 PCI Arbitration 8.1.1 Interrupt Routing for Devices Behind a BridgePCI-X Layout Guidelines Table 5. Interrupt Binding for Devices Behind a Bridge8.3 PCI General Layout Guidelines 8.2.1 PCI Resistor CompensationFigure 16. PCI RCOMP PCI-X Layout GuidelinesTable 6. PCI-X Signals 8.3.1 PCI Pullup Resistors Not RequiredTable 7. PCI/PCI-X Frequency/Mode Straps PCI-X Layout Guidelines8.4 PCI Clock Layout Guidelines PCI-X Layout GuidelinesFigure 17. PCI Clock Distribution and Matching Requirements PCI-X Layout GuidelinesIntel 41210 Bridge PCI Device PCI Device PCI Device PCI Device PCI DevicePCI-X Clock Layout Requirements Summary PCI-X Layout GuidelinesIntel 41210 Serial to Parallel PCI Bridge Design Guide ParameterPCI-X Layout Guidelines 8.5 PCI-X Topology Layout GuidelinesPCI-X Slot Guidelines 8.6.1 Embedded PCI-X 133 MHz Figure 18. Embedded PCI-X 133 MHz TopologyEmbedded PCI-X 133 MHz Routing Recommendations PCI-X Layout Guidelines8.6.2 Embedded PCI-X 100 MHz Figure 19. Embedded PCI-X 100 MHz TopologyEmbedded PCI-X 100 MHz Routing Recommendations PCI-X Layout Guidelines8.6.3 PCI-X 66 MHz Embedded Topology Figure 20. PCI-X 66 MHz Embedded Routing TopologyPCI-X 66 MHz Embedded Routing Recommendations PCI-X Layout Guidelines8.6.4 PCI 66 MHz Embedded Topology Figure 21. PCI 66 MHz Embedded TopologyPCI 66 MHz Embedded Table PCI-X Layout Guidelines8.6.5 PCI 33 MHz Embedded Mode Topology Figure 22. PCI 33 MHz Embedded Mode Routing TopologyPCI 33 MHz Embedded Routing Recommendations PCI-X Layout GuidelinesIntel 41210 Serial to Parallel PCI Bridge Design Guide This page intentionally left blankPCI-X Layout Guidelines PCI Express Layout 9.1 General recommendations9.2 PCI-Express Layout Guidelines 9.3 Adapter Card Layout GuidelinesPCI Express Layout Adapter Card Routing Recommendations Sheet 1 ofIntel 41210 Serial to Parallel PCI Bridge Design Guide Table 15. Adapter Card Routing Recommendations Sheet 2 ofPCI Express Layout Intel 41210 Serial to Parallel PCI Bridge Design Guide This page intentionally left blankPCI Express Layout Circuit Implementations 10.1 41210 Bridge Analog Voltage Filters10.1.1 PCI Analog Voltage Filters 10.1.2 PCI Express Analog Voltage FilterCircuit Implementations Figure 23. PCI Analog Voltage Filter CircuitCircuit Implementations 10.1.3 Bandgap Analog Voltage FilterFigure 24. PCI Express Analog Voltage Filter Circuit B2726 Bandgap Analog Voltage Filter CircuitCircuit Implementations Figure 26. Reference and Compensation Circuit Implementations Circuit ImplementationsCircuit Implementations Table 17. SMBUs Address Configuration10.2.1 SM Bus 41210 Bridge Customer Reference Boards11.1 Board Stack-up Intel 41210 Serial to Parallel PCI Bridge Design Guide11.2 Material 11.3 Impedance41210 Bridge Customer Reference Boards Table 18. CRB Board Stackup11.4 Board Outline Figure 27. Mechanical Outline of the 41210 Bridge41210 Bridge Customer Reference Boards U1 Intelﬁ BridgeIntel 41210 Serial to Parallel PCI Bridge Design Guide This page intentionally left blank41210 Bridge Customer Reference Boards Intel 41210 Serial to Parallel PCI Bridge Design Guide Design Guide ChecklistTable 19. PCI Express Interface Signals Intel 41210 Serial to Parallel PCI Bridge Design Guide Design Guide ChecklistTable 20. PCI/PCI-X Interface Signals Design Guide Checklist Table 20. PCI/PCI-X Interface SignalsIntel 41210 Serial to Parallel PCI Bridge Design Guide Design without secondary PCI/PCITable 21. Miscellaneous Signals Table 22. SMBus Interface SignalsDesign Guide Checklist To retry configuration accesses to the 41210, pull high toTable 23. Power and Ground Signals Design Guide Checklistpower down or any other time during system operation Intel 41210 Serial to Parallel PCI Bridge Design GuideIntel 41210 Serial to Parallel PCI Bridge Design Guide Table 24. JTAG SignalsDesign Guide Checklist