Bridge Reset and Power Timing Considerations | Intel 41210 guide

41210 Bridge Reset and Power Timing Considerations

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24	Intel® 41210 Serial to Parallel PCI Bridge Design Guide

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Intel 41210 manual Bridge Reset and Power Timing Considerations

Contents

Intel 41210 Serial to Parallel PCI Bridge Design Guide Intel 41210 Serial to Parallel PCI Bridge Design Guide Contents Figures Tables Revision HistoryDescription This page intentionally left blank About This Document Terminology and DefinitionsTerminology and Definitions Sheet 1 Term Definition About This Document Terminology and Definitions Sheet 2 PCI Express Interface Features PCI-X Interface FeaturesIntroduction2 Power Management SMBus for configuration register initializationSMBus Interface Introduction Bridge Microcontroller Block Diagram Microcontroller Connections to the 41210 Bridge Jtag Related Documents Intel 41210 Bridge Adapter Card Block Diagram Intel41210 Serial to Parallel PCI Bridge Applications This page intentionally left blank Package Specification Package Information Bottom View 41210 Bridge 567-Ball Fcbga Package Dimensions Package Information Side View 41210 Bridge 567-Ball Fcbga Package Dimensions This page intentionally left blank Power Plane Layout 41210 Bridge Decoupling Guidelines Power Plane Layout Split Voltage Planes Bridge Decoupling Guidelines PCI Bridge Reset and Power Timing Considerations5 ARST#,BRST# and PERST# Timing RequirementsVCC15 and VCC33 Voltage Requirements Bridge Reset and Power Timing Considerations General Routing Guidelines General Routing GuidelinesCrosstalk EMI Considerations General Routing Guidelines Power Distribution and Decoupling Trace ImpedanceDecoupling Differential Impedance Cross Section of Differential Trace Board Layout Guidelines Adapter Card TopologyAdapter Card Stack Up, Microstrip and Stripline Board Layout Guidelines Adapter Card Stackup PCI-X Layout Guidelines InterruptsINTx Routing Table PCI Arbitration Interrupt Routing for Devices Behind a BridgePCI-X Layout Guidelines Interrupt Binding for Devices Behind a Bridge PCI General Layout Guidelines PCI Resistor Compensation PCI-X Signals PCI Pullup Resistors Not RequiredPCI/PCI-X Frequency/Mode Straps PCI Clock Layout Guidelines BCBE#74, BDEVSEL#, BFRAME#, BINTA#, BINTB#, BINTC#, BINTD# PCI Clock Distribution and Matching Requirements PCI-X Clock Layout Requirements Summary Parameter Routing Guidelines PCI-X Topology Layout Guidelines PCI-X Slot Guidelines Embedded PCI-X 133 MHz Embedded PCI-X 133 MHz Routing RecommendationsParameter Routing Guideline for Lower AD Bus Embedded PCI-X 100 MHz Embedded PCI-X 100 MHz Routing Recommendations PCI-X 66 MHz Embedded Topology PCI-X 66 MHz Embedded Routing Recommendations PCI 66 MHz Embedded Topology PCI 66 MHz Embedded Table PCI 33 MHz Embedded Mode Topology PCI 33 MHz Embedded Routing Recommendations This page intentionally left blank PCI Express Layout General recommendations PCI-Express Layout Guidelines Adapter Card Layout GuidelinesPCI Express Layout Adapter Card Routing Recommendations Sheet 1 Adapter Card Routing Recommendations Sheet 2 This page intentionally left blank Config Circuit Implementations10.1 41210 Bridge Analog Voltage Filters PCI Analog Voltage Filters PCI Express Analog Voltage FilterCircuit Implementations Bandgap Analog Voltage Filter VccapeVssape Bandgap Analog Voltage Filter Circuit VccbgpeVSS Vssbgpe Reference and Compensation Circuit Implementations PERCOMP0 PERCOMP1 Rcomp SMBUs Address Configuration SM BusBit Value Bridge Customer Reference Boards Board Stack-up Layer Type Thickness Copper Weight MaterialImpedance Bridge Customer Reference Boards Board Outline Mechanical Outline of the 41210 Bridge This page intentionally left blank Design Guide Checklist PCI Express Interface SignalsSignals Recommendations Reason/Impact PERCOMP10 Design Guide Checklist PCI/PCI-X Interface Signals AM66EN BM66EN PERST#Apcixcap Bpcixcap Miscellaneous Signals SMBus Interface SignalsSignals Power and Ground Signals Signal Recommendations Reason/ImpactVCC15 VCC33 Jtag Signals