8399 N/B Maintenance

￿VDDSPD = +2.2V to +5.5V

￿2.5V I/O (SSTL_2 compatible)

￿Commands entered on each positive CK edge

￿DQS edge-aligned with data for READs; center-aligned with data for WRITEs

￿Internal, pipelined double data rate (DDR) architecture; two data accesses per clock cycle

￿Bidirectional data strobe (DQS) transmitted/receivedSecretDocumentwi h data—i. .,source-synchronous data capture

￿Differential clock inputs (CK and CK# - can be multiple clocks, CK0/CK0#, CK1/CK1#, etc.)

￿Four internal device banks for concurrent operation

￿Selectable burst lengths: 2,MiTac4, or 8

￿Auto prechargeConfidentialoption

￿Auto Refresh and Self Refresh Mod s

￿15.6μs (MT4VDDT864H, MT8VDDT1664HD), 7.8125μs (MT4VDDT1664H, MT8VDDT3264HD, MT8VDDT6464HD) maximum average periodic refresh interval

￿Serial Presence Detect (SPD) with EEPROM

￿Fast data transfer rates PC2700, PC2100 or PC1600

￿Selectable READ CAS latency for maximum compatibility

￿Gold-plated edge contacts

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