8399 N/B Maintenance
5.3 VIA VT8235CD South Bridge(9)Power Management and Event Detection (Continued) |
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| Power Management and Event Detection (Continued) |
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Signal Name | Pin # | I/O | Signal Description |
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| Signal Name | Pin # | I/O | Signal Description |
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LID# / GPI4 | AC1 | I | Notebook Computer Display Lid Open / Closed |
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| SUSST1# / | Y3 | O | Suspend Status 1 (Rx94[4] = 0). Typically connected to | ||
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| Monitor. Used by the Power Management subsystem to |
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| GPO3 |
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| the North Bridge to provide information on host clock | ||
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| monitor the opening and closing of the display lid of |
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| status. Asserted when the system may stop the host clock, | ||
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| notebook computers. Can be used to detect either |
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| such as Stop Clock or during POS, STR, or STD suspend | ||
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| states. Connect 10K PU to VSUS33. | ||||
INTRUDER# / |
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| (10K PU to VSUS33 if not used) |
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| SUSCLK | AB3 | O | Suspend Clock. 32.768 KHz output clock for use by the | ||
AE1 | I | Intrusion Indicator. The value of this bit may be read at |
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| North Bridge (e.g., KT400A, CLE266, or P4X400) for | |||
GPI16 |
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| PMIO Rx20[6] |
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| DRAM refresh purposes. Stopped during | |
THRM# / GPI18/ | Y4 | I | Thermal Alarm Monitor. Rx8C[3] = 1. Rising or falling |
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| and | ||
AOLGPI |
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| edges (selectable by PMIORx2C[6]) may be detected to set |
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| CPUMISS / | Y1 | I | CPU Missing. Used to detect the physical presence of the | ||
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| status at PMIO Rx20[10]. Setting of this status bit |
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| GPI17 |
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| CPU chip in its socket. |
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| may then be used to generate an SCI or SMI. THRM# may | Secret |
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| High indicates no CPU present. Connect to the CPUMISS | ||||
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| also be used to enable duty cycle control of |
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| pin of the CPU socket. The state of this pin may be read in | |||||
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| (STPCLK#) to automatically limit maximum temperature |
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| the SMBus 2 registers. This pin may be used as CPUMISS | |||||
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| (see Device 17 Function 0 |
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| and GPI17 at the same time. |
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RING# / GPI3 | Y2 | I | Ring Indicator. May be connected to external modem |
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| AOLGPI / | Y4 | I | Alert On LAN. The state of this pin may be read in the | ||
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| circuitry to allow the system to be |
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| GPI18/ THRM# |
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| SMBus 2 registers. This pinmay be used as AOLGPI, | ||
BATLOW# / | V4 | I | received phone call. (10K PU to VSUS33 not used) |
| DocumentGPI18 and THRM# all at the same time. | ||||||
Battery Low Indicator. (10K PU to VSUS33 if not used) |
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GPI5 |
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| (3.3V only) |
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CPUSTP# / | AC7 | O | CPU Clock Stop (RxE4[0] = 0). Signals the system clock |
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GPO5 |
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| MiTac |
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| generator to disable the CPU clock outputs. Not co ected |
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| Strap Pins for VT8235 Version CE Configuration |
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| if not used. |
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| Note | ||||
PCISTP# / | AD6 | O | PCI Clock Stop (RxE4[1] = 0). S gnals the system clock |
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| Signal Name | Pin # | Function | Description | ||
GPO6 |
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| generator to disable the PCI clock outputs. Not connected if |
| Strap_AUTO | AE10 | Auto | L: Enable Auto Reboot |
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| not used. |
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| Reboot | H: Disable Auto Reboot |
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SUSA# / GPO1 | AA2 | O | Suspend Plane A Control (Rx94[2]=0). Asserted during |
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| (Default) |
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| power management POS, STR, and STD suspend states. |
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| SPKR | AF8 | CPU | L: Enable CPU Frequency |
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| Used to control the primary power plane. (10K PU to |
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| Frequency | Strapping |
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SUSB# / GPO2 | AD3 | O | VSUS33 if notConfidentialused) |
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| Strapping H: Disable CPU Frequency |
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Suspend Plane B Control (Rx94[3]=0). Asserted during |
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| Strapping (Default) |
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| power management STR and STD suspend states. Used to |
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| KBCS# | AF10 | Internal | L: Disable internal KBC |
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| control the secondary power plane. (10K PU to VSUS33 |
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| Keyboard | H: Enable internal KBC |
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| if not used) |
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| Controller | (Default) |
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SUSC# | AF2 | O | Suspend Plane C Control. Asserted during power |
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| SDCS1# | AF25 | Eliminate | L: Enable. Use external |
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| management STD suspend state. |
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| External | EEPROM (Default) |
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| Used to control the tertiary power plane. Also connected to |
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| LAN | H: Disable. Do not use |
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| ATX |
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| EEPROM | external EEPROM |
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