8399 N/B Maintenance

5.3 VIA VT8235CD South Bridge(9)

Power Management and Event Detection (Continued)

 

 

 

Power Management and Event Detection (Continued)

 

Signal Name

Pin #

I/O

Signal Description

 

 

 

Signal Name

Pin #

I/O

Signal Description

 

LID# / GPI4

AC1

I

Notebook Computer Display Lid Open / Closed

 

 

SUSST1# /

Y3

O

Suspend Status 1 (Rx94[4] = 0). Typically connected to

 

 

 

Monitor. Used by the Power Management subsystem to

 

 

GPO3

 

 

the North Bridge to provide information on host clock

 

 

 

monitor the opening and closing of the display lid of

 

 

 

 

 

status. Asserted when the system may stop the host clock,

 

 

 

notebook computers. Can be used to detect either

 

 

 

 

 

such as Stop Clock or during POS, STR, or STD suspend

 

 

 

low-to-high or high-to-low transitions to generate an SMI#.

 

 

 

 

states. Connect 10K PU to VSUS33.

INTRUDER# /

 

 

(10K PU to VSUS33 if not used)

 

 

SUSCLK

AB3

O

Suspend Clock. 32.768 KHz output clock for use by the

AE1

I

Intrusion Indicator. The value of this bit may be read at

 

 

 

 

 

North Bridge (e.g., KT400A, CLE266, or P4X400) for

GPI16

 

 

PMIO Rx20[6]

 

 

 

 

 

 

DRAM refresh purposes. Stopped during Suspend-to-Disk

THRM# / GPI18/

Y4

I

Thermal Alarm Monitor. Rx8C[3] = 1. Rising or falling

 

 

 

 

 

and Soft-Off modes. Connect 10K PU to VSUS33.

AOLGPI

 

 

edges (selectable by PMIORx2C[6]) may be detected to set

 

 

CPUMISS /

Y1

I

CPU Missing. Used to detect the physical presence of the

 

 

 

status at PMIO Rx20[10]. Setting of this status bit

 

 

GPI17

 

 

CPU chip in its socket.

 

 

 

 

may then be used to generate an SCI or SMI. THRM# may

Secret

 

 

High indicates no CPU present. Connect to the CPUMISS

 

 

 

also be used to enable duty cycle control of stop-clock

 

 

pin of the CPU socket. The state of this pin may be read in

 

 

 

(STPCLK#) to automatically limit maximum temperature

 

 

the SMBus 2 registers. This pin may be used as CPUMISS

 

 

 

(see Device 17 Function 0 Rx8C[7-4]).

 

 

and GPI17 at the same time.

 

 

 

 

 

 

 

 

 

 

RING# / GPI3

Y2

I

Ring Indicator. May be connected to external modem

 

 

AOLGPI /

Y4

I

Alert On LAN. The state of this pin may be read in the

 

 

 

circuitry to allow the system to be re-activated by

 

 

GPI18/ THRM#

 

 

SMBus 2 registers. This pinmay be used as AOLGPI,

BATLOW# /

V4

I

received phone call. (10K PU to VSUS33 not used)

 

DocumentGPI18 and THRM# all at the same time.

Battery Low Indicator. (10K PU to VSUS33 if not used)

 

 

 

 

 

 

 

GPI5

 

 

(3.3V only)

 

 

 

 

 

 

 

 

CPUSTP# /

AC7

O

CPU Clock Stop (RxE4[0] = 0). Signals the system clock

 

 

 

 

 

 

 

GPO5

 

 

 

MiTac

 

 

 

 

 

 

 

 

generator to disable the CPU clock outputs. Not co ected

 

 

Strap Pins for VT8235 Version CE Configuration

 

 

 

 

if not used.

 

 

 

Note

PCISTP# /

AD6

O

PCI Clock Stop (RxE4[1] = 0). S gnals the system clock

 

 

Signal Name

Pin #

Function

Description

GPO6

 

 

generator to disable the PCI clock outputs. Not connected if

 

Strap_AUTO

AE10

Auto

L: Enable Auto Reboot

 

 

 

 

not used.

 

 

 

 

 

Reboot

H: Disable Auto Reboot

 

SUSA# / GPO1

AA2

O

Suspend Plane A Control (Rx94[2]=0). Asserted during

 

 

 

 

 

(Default)

 

 

 

 

power management POS, STR, and STD suspend states.

 

 

SPKR

AF8

CPU

L: Enable CPU Frequency

 

 

 

 

Used to control the primary power plane. (10K PU to

 

 

 

 

Frequency

Strapping

 

SUSB# / GPO2

AD3

O

VSUS33 if notConfidentialused)

 

 

Strapping H: Disable CPU Frequency

 

Suspend Plane B Control (Rx94[3]=0). Asserted during

 

 

 

 

 

Strapping (Default)

 

 

 

 

power management STR and STD suspend states. Used to

 

 

KBCS#

AF10

Internal

L: Disable internal KBC

 

 

 

 

control the secondary power plane. (10K PU to VSUS33

 

 

 

 

Keyboard

H: Enable internal KBC

 

 

 

 

if not used)

 

 

 

 

 

Controller

(Default)

 

SUSC#

AF2

O

Suspend Plane C Control. Asserted during power

 

 

SDCS1#

AF25

Eliminate

L: Enable. Use external

 

 

 

 

management STD suspend state.

 

 

 

 

External

EEPROM (Default)

 

 

 

 

Used to control the tertiary power plane. Also connected to

 

 

 

 

LAN

H: Disable. Do not use

 

 

 

 

ATX power-on circuitry. (10K PU to VSUS33 if not used)

 

 

 

 

EEPROM

external EEPROM

 

88