8399 N/B Maintenance
5.2 VIA K8N800 North Bridge(5)Signal Name |
| AGP Name | Pin # | I/O | Signal Description |
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| Signal Name | AGP Name | Pin # | I/O |
GTVD11 / GDVP1D11, | GC#BE3 | AC7 | O | Data. |
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| FPD23 / FPD0D11, | GD11 | AE13 | O | ||
GTVD10 / GDVP1D10, | GD26 | AE6 |
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| FPD22 / FPD0D10, | GD13 | AD12 |
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GTVD9 / GDVP1D9, |
| GD24 | AF6 |
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| FPD21 / FPD0D09, | GD14 | AF12 |
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GTVD8 / GDVP1D8, |
| GD30 | AE4 |
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| FPD20 / FPD0D08, | GD15 | AE12 |
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GTVD7 / GDVP1D7, |
| GD28 | AF5 |
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| FPD19 / FPD0D07, | GC#BE2 | AD11 |
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GTVD6 / GDVP1D6, |
| GD29 | AF4 |
| pulled down. |
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| FPD18 / FPD0D06, | GD16 | AD10 |
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GDVP1DET |
| GSBA4# | AF2 |
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| DocumentFPD06 / FPD1D06, GD5 AE16 |
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GTVD5 / GDVP1D5, |
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| FPD17 / FPD0D05, | GD17 | AE10 |
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GTVD4 / GDVP1D4, |
| GD27 | AD5 |
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| FPD16 / FPD0D04, | GD18 | AF10 |
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GTVD3 / GDVP1D3, |
| GSBA5# | AD3 |
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| SecretFPD09 / FPD1D09, | GD0 | AF17 |
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| FPD15 / FPD0D03, | GD23 | AD8 |
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GTVD2 / GDVP1D2, |
| GSBSTBS | AE1 |
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| FPD14 / FPD0D02, | GD20 | AF9 |
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GTVD1 / GDVP1D1, |
| GSBSTBF | AF1 |
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| FPD13 / FPD0D01, | GD22 | AE9 |
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GTVD0 / GDVP1D0 |
| GSBA2# | AD1 |
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| FPD12 / FPD0D00, | GADSSTB1 | AE7 |
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GTVHS / GDVP1HS |
| GSBA3# | AD2 | O | Horizontal Sync. Internally pulled down. |
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| FPD11 / FPD1D11, | F | AD18 |
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GTVVS / GDVP1VS |
| GSBA0# | AC2 | O | Vertical Sync. Internally pulled down. |
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| FPD10 / FPD1D10, | GD1 | AF18 |
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| MiTac |
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GTVDE / GDVP1DE |
| GSBA1# | AC3 | O | Display Enable. Internally pulled down. |
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| FP | 08 / FPD1D08, | GD3 | AD17 |
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GTVCLKR | / | GD31 | AD4 | I | Clock In. Input from TV encoder. Intern lly |
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| FP | 07 / FPD1D07, | GD4 | AD16 |
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GTVCLK | / | GSBA6# | AE3 | O | Confidential | FPDE | GD19 | AD9 | O | ||||
Clock Out. Output to TV encoder. Internally |
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| FPD05 / FPD1D05, | GD6 | AF16 |
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GDVP1CLK |
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| pulled down. |
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| FPD04 / FPD1D04, | GD7 | AE15 |
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GTVCLK# | / | GSBA7# | AF3 | O | Clock Out Complement. Output to TV |
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| FPD03 / FPD1D03, | GADSTB0F AD15 |
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GDVP1CLK# |
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| encoder. Internally pulled down. |
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| FPD02 / FPD1D02, | GC#BE0 | AF15 |
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The above pins may be connected to an external TV Encoder chip such as VIA VT1623 or |
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| FPD01 / FPD1D01, | GADSTB0S | AD13 |
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VT1623M for driving a TV set. |
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| FPD00 / FPD1D00 | GD10 | AF13 |
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I/O pads for the pins on this page are powered by VCC15AGP (1.5V I/O). |
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| GD12 |
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| FPHS | GFRAME | AC9 | O | |
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| FPVS | GDEVSEL | AC11 | O | |
Flat Panel Power Control (Muxed with AGP) |
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| FPDET | GADSTB1S | AF7 | I | ||||||
Signal Name |
| AGP Name | Pin # | I/O | Signal Description |
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| FPCLK | GD21 | AF8 | O | |
ENAVDD |
| GST1 | AA1 | IO | Enable Panel VDD Power. |
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ENAVEE |
| GST0 | AA2 | IO | Enable Panel VEE Power. |
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| FPCLK# | GWBF | AC1 | O | ||
ENABLT |
| GST2 | AB1 | IO | Enable Panel Back Light. |
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Note: I/O pads for all pins on this page are powered by VCC15AGP (i.e., 1.5V I/O).
Signal Description
Flat Panel Data. For
Two FPD interface modes,
Strapping pin DVP0D4 is used to select the interface mode to the LVDS transmitter chip: Strap High (3C5.12[4]=1):
Strap Low (3C5.12[4]=0): Dual
In
In
3C5.12[4]=1 & 3x5.88[2]=0 & 3x5.88[4]=0 Double data rate: each rising & falling clock edge transmits a complete
In dual
Each rising and falling clock edge transmits half (12 bits) of two
Flat Panel Horizontal Sync.
Flat Panel Vertical Sync.
Flat Panel Data Enable.
of dual
Flat Panel Detect.
Flat Panel Clock.
Flat Panel Clock Complement.
Mode.
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