8399 N/B Maintenance

5.2 VIA K8N800 North Bridge(5)

AGP-Multiplexed Digital Video Port 1 (GDVP1) – TV Encoder

24-Bit / Dual 12-Bit Flat Panel Display Interface

Signal Name

 

AGP Name

Pin #

I/O

Signal Description

 

 

 

 

Signal Name

AGP Name

Pin #

I/O

GTVD11 / GDVP1D11,

GC#BE3

AC7

O

Data.

 

 

 

FPD23 / FPD0D11,

GD11

AE13

O

GTVD10 / GDVP1D10,

GD26

AE6

 

 

 

 

 

FPD22 / FPD0D10,

GD13

AD12

 

GTVD9 / GDVP1D9,

 

GD24

AF6

 

 

 

 

 

FPD21 / FPD0D09,

GD14

AF12

 

GTVD8 / GDVP1D8,

 

GD30

AE4

 

 

 

 

 

FPD20 / FPD0D08,

GD15

AE12

 

GTVD7 / GDVP1D7,

 

GD28

AF5

 

 

 

 

 

FPD19 / FPD0D07,

GC#BE2

AD11

 

GTVD6 / GDVP1D6,

 

GD29

AF4

 

pulled down.

 

 

 

FPD18 / FPD0D06,

GD16

AD10

 

GDVP1DET

 

GSBA4#

AF2

 

 

 

DocumentFPD06 / FPD1D06, GD5 AE16

 

GTVD5 / GDVP1D5,

 

 

 

 

 

 

FPD17 / FPD0D05,

GD17

AE10

 

GTVD4 / GDVP1D4,

 

GD27

AD5

 

 

 

 

 

FPD16 / FPD0D04,

GD18

AF10

 

GTVD3 / GDVP1D3,

 

GSBA5#

AD3

 

 

 

SecretFPD09 / FPD1D09,

GD0

AF17

 

 

 

 

 

 

 

FPD15 / FPD0D03,

GD23

AD8

 

GTVD2 / GDVP1D2,

 

GSBSTBS

AE1

 

 

 

 

 

FPD14 / FPD0D02,

GD20

AF9

 

GTVD1 / GDVP1D1,

 

GSBSTBF

AF1

 

 

 

 

 

FPD13 / FPD0D01,

GD22

AE9

 

GTVD0 / GDVP1D0

 

GSBA2#

AD1

 

 

 

 

 

FPD12 / FPD0D00,

GADSSTB1

AE7

 

GTVHS / GDVP1HS

 

GSBA3#

AD2

O

Horizontal Sync. Internally pulled down.

 

 

FPD11 / FPD1D11,

F

AD18

 

GTVVS / GDVP1VS

 

GSBA0#

AC2

O

Vertical Sync. Internally pulled down.

 

 

FPD10 / FPD1D10,

GD1

AF18

 

 

 

 

 

 

 

MiTac

 

 

 

 

 

 

GTVDE / GDVP1DE

 

GSBA1#

AC3

O

Display Enable. Internally pulled down.

 

 

FP

08 / FPD1D08,

GD3

AD17

 

GTVCLKR

/

GD31

AD4

I

Clock In. Input from TV encoder. Intern lly

 

 

FP

07 / FPD1D07,

GD4

AD16

 

GTVCLK

/

GSBA6#

AE3

O

Confidential

FPDE

GD19

AD9

O

Clock Out. Output to TV encoder. Internally

 

 

FPD05 / FPD1D05,

GD6

AF16

 

GDVP1CLK

 

 

 

 

pulled down.

 

 

 

FPD04 / FPD1D04,

GD7

AE15

 

GTVCLK#

/

GSBA7#

AF3

O

Clock Out Complement. Output to TV

 

 

FPD03 / FPD1D03,

GADSTB0F AD15

 

GDVP1CLK#

 

 

 

 

encoder. Internally pulled down.

 

 

FPD02 / FPD1D02,

GC#BE0

AF15

 

The above pins may be connected to an external TV Encoder chip such as VIA VT1623 or

 

 

FPD01 / FPD1D01,

GADSTB0S

AD13

 

VT1623M for driving a TV set.

 

 

 

 

 

 

FPD00 / FPD1D00

GD10

AF13

 

I/O pads for the pins on this page are powered by VCC15AGP (1.5V I/O).

 

 

 

 

 

GD12

 

 

 

 

 

 

 

 

 

 

 

FPHS

GFRAME

AC9

O

 

 

 

 

 

 

 

 

 

FPVS

GDEVSEL

AC11

O

Flat Panel Power Control (Muxed with AGP)

 

 

 

FPDET

GADSTB1S

AF7

I

Signal Name

 

AGP Name

Pin #

I/O

Signal Description

 

 

 

FPCLK

GD21

AF8

O

ENAVDD

 

GST1

AA1

IO

Enable Panel VDD Power.

 

 

 

 

 

 

 

 

 

 

ENAVEE

 

GST0

AA2

IO

Enable Panel VEE Power.

 

 

FPCLK#

GWBF

AC1

O

ENABLT

 

GST2

AB1

IO

Enable Panel Back Light.

 

 

 

 

 

 

 

 

 

 

Note: I/O pads for all pins on this page are powered by VCC15AGP (i.e., 1.5V I/O).

Signal Description

Flat Panel Data. For 24-bit or dual 12-bit flat panel display modes.

Two FPD interface modes, 24-bit and dual 12-bit, are supported.

Strapping pin DVP0D4 is used to select the interface mode to the LVDS transmitter chip: Strap High (3C5.12[4]=1): 24-bit

Strap Low (3C5.12[4]=0): Dual 12-bit

In in24-bitl] mode, only one set of control pins is required. However, in dual 12-bit mode, the K8N800 Version CD provides two sets of control signals that are required for certain LVDS transmitter chips.

In 24-bit mode, two operating modes are supported:

3C5.12[4]=1 & 3x5.88[2]=0 & 3x5.88[4]=0 Double data rate: each rising & falling clock edge transmits a complete 24-bit pixel 3C5.12[4]=1 & 3x5.88[2]=0 & 3x5.88[4]=1 Single data rate: each clock rising edge transmits a complete 24-bit pixel

In dual 12-bit mode, 3C5.12[4]=0 & 3x5.88[2] = 1

Each rising and falling clock edge transmits half (12 bits) of two 24-bit pixels

Flat Panel Horizontal Sync. 24-bit mode or port 0 of dual 12-bit mode.

Flat Panel Vertical Sync. 24-bit mode or port 0 of dual 12-bit mode.

Flat Panel Data Enable. 24-bit mode or port 0

of dual 12-bit mode

Flat Panel Detect. 24-bit mode or port 0 of dual 12-bit mode

Flat Panel Clock. 24-bit mode or port 0 of dual 12-bit mode

Flat Panel Clock Complement. 24-bit mode or port 0 of dual 12-bit

Mode.

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