8399 N/B Maintenance
5.2 VIA K8N800 North Bridge(4)Dedicated Digital Video Port 0 (DVP0) - TV Encoder Interface |
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Signal Name | Pin # | I/O | Signal Description |
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| Signal Name | AGP Name | Pin # | I/O | Signal Description | |||
TVD11 / DVP0D11 | M1 | O | TV Encoder 0 Data. |
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| GDVP1D11 | GC#BE3 |
| AC7 | O | Data. | ||
TVD10 / DVP0D10 | M3 |
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| GDVP1D10 | GD26 |
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| AE6 |
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TVD9 / DVP0D9 | M2 |
| To configure DVP0 as a TV Out interface port, pins |
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| GDVP1D9 | GD24 |
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| AF6 |
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TVD8 / DVP0D8 | L1 |
| DVP0D[6:5] must be strapped high. |
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| GDVP1D8 | GD30 |
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| AE4 |
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TVD7 / DVP0D7 | M4 |
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| GDVP1D7 | GD28 |
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| AF5 |
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TVD6 / DVP0D6 | L3 |
| Note: One TV Encoder interface is supported through either |
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| GDVP1D6 | GD29 |
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| AF4 |
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TVD5 / DVP0D5 | L2 |
| DVP0 or GDVP1. |
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| GDVP1D5 | GSBA4# |
| AF2 |
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TVD4 / DVP0D4 | K1 |
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| GDVP1D4 | GD27 |
| AD5 |
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TVD3 / DVP0D3 | L4 |
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| GDVP1D3 | GSBA5# | AD3 |
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TVD2 / DVP0D2 | K3 |
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| GDVP1D2 | GSBSTBS |
| AE1 |
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TVD1 / DVP0D1 | K2 |
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| GDVP1D1 | GSBSTBF |
| AF1 |
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TVD0 / DVP0D0 | J1 |
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| GDVP1D0 | GSBA2# | AD1 |
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TVHS / DVP0HS | N4 | O | TV Encoder 0 Horizontal Sync. Internally pulled down. |
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| GDVP1HS | GSBA3# | AD2 | O | Horizontal Sync. | ||||
TVVS / DVP0VS | N3 | O | TV Encoder 0 Vertical Sync. Internally pulled down. |
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| GDVP1VS | GSBA0# |
| AC2 | O | Vertical Sync. | |||
TVDE / DVP0DE | N1 | O | TV Encoder 0 Display Enable. Internally pulled down. | Secret | GSBA1# |
| AC3 | O | Data Enable. | |||||
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| GDVP1DE |
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TVCLKR / DVP0DET | P4 | I | TV Encoder 0 Clock Return. Input from TV encoder. |
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| G VP1DET | GD31 |
| AD4 | I | Display Detect. If VGA register 3C5.3E[0] = 1, | |||
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| Internally pulled |
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| Document |
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| 3C5.1A[4] will read 1 if a display is connected. | ||||
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| down. |
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| GSBA6# |
| AE3 | O | Tie to GND if not used. | |
TVCLK / DVP0CLK | P3 | O | TV Encoder 0 Clock Out. Output to TV encoder. In ernally |
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| GDVP1CLK |
| Clock. | ||||||
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| pulled |
| MiTac |
| GDVP1CLK# | GSBA7# |
| AF3 | O | Clock Complement. | ||
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| down. |
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| The GDVP1 Digital Video Port is supported through multiplexing its interface signal pins with AGP | ||||||
The above pins may be connected to an external TV Encoder chip such as | VIA VT1622A or |
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| pins. GDVP1 can be configured as either a TMDS transmitter interface port or a TV Encoder interface | ||||||||||||
VT1622AM for driving a TV set. |
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| port. (see the TMDS Transmitter Interface and TV Encoder Interface pin lists below for details). | ||||||||
I/O pads for the pins on this page are powered by VCCGFX (3.3V I/O). |
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Analog Power / Ground |
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| Reference Voltages |
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Signal Name | Pin # | I/O | Signal Description |
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VCCATX | C22 | P |
| Confidential | VLVREF | AF21 | P | |||||||
Analog Power for HT Transmit. 3.3V ±5%. Connect |
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| through a ferrite bead for isolation of digital switching noise. |
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| resistive voltage divider (3K §Ù to | |||||
GNDATX | C21 | P | Analog Ground for HT Transmit. Connect to main ground |
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| 2.5V and 1K §Ù to ground). See Design Guide for details. | |||||
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| plane through a ferrite bead for isolation of digital switching |
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| AGPVREF[1:0] | AC6, | P | AGP Voltage Reference. 0.5 VCCQQ (0.75V) for AGP 2.0 | |||||
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| noise. |
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| AC13 |
| (4x transfer mode) and 0.23 VCCQQ (0.35V) for AGP 3.0 (8x | |||
VCCARX | E25 | P | Analog Power for HT Receive. 3.3V ±5%. Connect through |
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| transfer mode). See the Design Guide for additional | |||||
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| a ferrite bead for isolation of digital switching noise. |
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| information and circuit implementation details.. | |||||
GNDARX | E26 | P | Analog Ground for HT Receive. Connect to main ground |
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| plane through a ferrite bead for isolation of digital switching |
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| noise. |
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