8399 N/B Maintenance

5.3 VIA VT8235CD South Bridge(1)

V-Link Interface

Signal Name

Pin #

I/O

VD[7:0]

(see pin

IO

 

list)

 

VPAR

F24

IO

VBE#

G24

IO

VCLK

L22

I

UPCMD

K23

O

DNCMD

K25

I

UPSTB

J26

O

UPSTB#

J24

O

DNSTB

K26

I

DNSTB#

H24

I

Signal Description

 

 

 

 

CPU Interface

 

 

 

 

 

 

Signal Name

Pin #

I/O

Signal Description

Data Bus. These pins are also used to send strap information to

 

 

A20M#

U26

OD

A20 Mask. Connect to A20 mask input of the CPU to control

the chipset north

 

 

 

 

 

 

 

 

address bit-20 generation.

bridge. At power up, VD7 reflects the state of a strap on

 

 

 

 

 

Logical combination of the A20GATE input (from internal or

SDCS3#, VD[6:4] reflect

 

 

 

 

 

 

 

external keyboard controller)

the state of straps on pins SDA[2:0], and VD[3:0] reflect the

 

 

 

 

 

and Port 92 bit-1 (Fast_A20).

state of straps on pins

 

 

 

 

FERR#

U24

I

Numerical Coprocessor Error. This signal is tied to the

Strap_VD3-0. The specific interpretation of these straps is north

 

 

 

 

coprocessor error signal on the

bridge chip design

 

 

 

 

 

 

 

 

CPU. Internally generates interrupt 13 if active. Output voltage

dependent.

 

 

 

 

 

 

 

 

swing is programmable tot

Parity. If the VPAR function is implemented in a compatible

 

 

 

 

 

1.5V or 2.5V by Device 17 Function 0 Rx67[2].

manner on the north

 

 

 

 

IGNNE#

T24

OD

Ignore Numeric Error. This pin is connected to the CPU

bridge, this pin should be connected to the north bridge VPAR

 

 

 

 

 

iPignore errorlr pin.

pin (P4X333,

 

 

 

 

 

INIT#

R26

OD

Initialization. The VT8235 Version CE asserts INIT# if it

P4X400, P4X800, KT400). If VPAR is not implemented in the

Secret

 

 

detects a shut-down special

north bridge chip or

 

 

 

 

cycle on the PCI bus or if a soft reset is initiated by the register

is incompatible with the 8235CE (4x V-Link north bridges)

 

 

INTR

T25

OD

CPU Interrupt. INTR is driven by the VT8235 Version CE to

connect this pin to an

 

 

 

 

 

 

 

signal the CPU that an

8.2K pullup to 2.5V (Pro266, Pro266T, KT266, K

266A,

 

Documentinterrupt request is pending and needs service.

KT333, P4X266, PN266,

 

 

 

 

NMI

T26

OD

Non-Maskable Interrupt. NMI is used to force a

KN266, KM266, P4M266, P4N266). See app note AN222 for

 

 

 

 

 

non-maskable interrupt to the CPU. The

details.

 

MiTac

 

 

 

 

VT8235 Version CE generates an NMI when PCI bus SERR# is

Byte Enable.

 

 

 

 

 

asserted.

 

 

 

 

 

 

 

 

V-Link Clock.

 

 

 

 

 

SLP#

V26

OD

Sleep. Used to put the CPU to sleep.

Command from Client-to-Host.

 

 

 

 

SMI#

U25

OD

System Management Interrupt. SMI# is asserted by the

Command from Host-to-Client.

 

 

 

 

 

 

 

VT8235 Version CE to the CPU

 

 

 

 

 

 

 

in response to different Power-Management events.

Strobe from Client-to-H st.

 

 

 

 

 

 

 

 

 

 

 

STPCLK#

R24

OD

Stop Clock. STPCLK# is asserted by the VT8235 Version CE

Complement Strobe fr m Client-to-Host.

 

 

 

 

 

 

to the CPU to throttle the

Strobe from Host-to- lient.

 

 

 

 

 

 

 

processor clock.

 

 

 

 

Note: Connect each of the above signals to 150 §Ù pullup resistors to VCC_CMOS (see Design Guide).

 

Confidential

 

 

 

 

 

Complement Strobe from Host-to-Client.

 

 

 

 

 

 

 

80