8399 N/B Maintenance
5.3 VIA VT8235CD South Bridge(1)Signal Name | Pin # | I/O |
VD[7:0] | (see pin | IO |
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VPAR | F24 | IO |
VBE# | G24 | IO |
VCLK | L22 | I |
UPCMD | K23 | O |
DNCMD | K25 | I |
UPSTB | J26 | O |
UPSTB# | J24 | O |
DNSTB | K26 | I |
DNSTB# | H24 | I |
Signal Description |
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| CPU Interface |
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| Signal Name | Pin # | I/O | Signal Description | ||
Data Bus. These pins are also used to send strap information to |
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| A20M# | U26 | OD | A20 Mask. Connect to A20 mask input of the CPU to control | |||
the chipset north |
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bridge. At power up, VD7 reflects the state of a strap on |
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| Logical combination of the A20GATE input (from internal or | |||
SDCS3#, VD[6:4] reflect |
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| external keyboard controller) | |
the state of straps on pins SDA[2:0], and VD[3:0] reflect the |
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| and Port 92 | |||
state of straps on pins |
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| FERR# | U24 | I | Numerical Coprocessor Error. This signal is tied to the | |
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| coprocessor error signal on the | |||||
bridge chip design |
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| CPU. Internally generates interrupt 13 if active. Output voltage |
dependent. |
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| swing is programmable tot |
Parity. If the VPAR function is implemented in a compatible |
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| 1.5V or 2.5V by Device 17 Function 0 Rx67[2]. | |||
manner on the north |
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| IGNNE# | T24 | OD | Ignore Numeric Error. This pin is connected to the CPU | |
bridge, this pin should be connected to the north bridge VPAR |
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| iPignore errorlr pin. | |||
pin (P4X333, |
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| INIT# | R26 | OD | Initialization. The VT8235 Version CE asserts INIT# if it |
P4X400, P4X800, KT400). If VPAR is not implemented in the | Secret |
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north bridge chip or |
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| cycle on the PCI bus or if a soft reset is initiated by the register | ||||
is incompatible with the 8235CE (4x |
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| INTR | T25 | OD | CPU Interrupt. INTR is driven by the VT8235 Version CE to | |||
connect this pin to an |
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| signal the CPU that an | |
8.2K pullup to 2.5V (Pro266, Pro266T, KT266, K | 266A, |
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KT333, P4X266, PN266, |
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| NMI | T26 | OD | ||
KN266, KM266, P4M266, P4N266). See app note AN222 for |
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details. |
| MiTac |
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| VT8235 Version CE generates an NMI when PCI bus SERR# is | ||
Byte Enable. |
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| SLP# | V26 | OD | Sleep. Used to put the CPU to sleep. | |
Command from |
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| SMI# | U25 | OD | System Management Interrupt. SMI# is asserted by the | |
Command from |
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| VT8235 Version CE to the CPU | |
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Strobe from |
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| STPCLK# | R24 | OD | Stop Clock. STPCLK# is asserted by the VT8235 Version CE | ||
Complement Strobe fr m |
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| to the CPU to throttle the | ||
Strobe from |
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| processor clock. | |
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| Note: Connect each of the above signals to 150 §Ù pullup resistors to VCC_CMOS (see Design Guide). | |||||
| Confidential | ||||||||
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Complement Strobe from |
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