8399 N/B Maintenance
5.3 VIA VT8235CD South Bridge(5)Signal Name | Pin # | I/O Signal Description | Signal Name | Pin # | I/O Signal Description | ||
PDRDY | Y22 | I | EIDE Mode: Primary I/O Channel Ready. Device ready | PDDACK# | Y24 | O | Primary Device DMA Acknowledge. Primary channel DMA |
/PDDMARDY |
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| indicator UltraDMA Mode: Primary Device DMA Ready. |
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| acknowledge |
/PDSTROBE |
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| Output flow control. The device mayassert DDMARDY to pause | SDDACK# | AD23 | O | Secondary Device DMA Acknowledge. Secondary channel DMA |
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| output transfers Primary Device Strobe. Input data strobe (both |
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| acknowledge |
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| edges). The device may stop DSTROBE to pause input data | IRQ14 | AD24 | I | Primary Channel Interrupt Request. |
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| transfers | IRQ15 | AE26 | I | Secondary Channel Interrupt Request. |
SDIOR# | AF23 | O | EIDE Mode: Secondary Device I/O Read. Dev ce read strobe | Document | |||
SDRDY | AF17 | I | EIDE Mode: Secondary I/O Channel Ready. Device ready | PDCS1# | V22 | O | Primary Master Chip Select. This signal corresponds to CS1FX# |
/SDDMARDY |
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| indicator UltraDMA Mode: Secondary Device DMA Ready. | ||||
/PHSTROBE |
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| input flow control. Thehost may assert HDMARDY to pause input Secret |
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| disables the EExx pins). This pin has an internal pullup to default to | |
/SDSTROBE |
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| Output flow control. The devicemay assert DDMARDY to pause |
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| on the primary IDE connector. |
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| output transfers Secondary Device Strobe. Input data strobe (both | PDCS3# | V23 | O | Primary Slave Chip Select. This signal corresponds to CS3FX# on |
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| edges). The device may stop DSTROBE to pause input data |
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| the primary IDE connector. |
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| transfers | SDCS1# / strap | AF25 | O | Secondary Master Chip Select. This signal corresponds to |
PDIOR# | W26 | O | EIDE Mode: Primary Device I/O Read. Device read strobe |
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| CS17X# on the secondary IDE connector. Strap low (resistor to |
/PHDMARDY |
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| UltraDMA Mode: Primary Host DMA Ready. Primary channel |
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| ground) to enable serial EEPROM interface via the MII bus (this |
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| MiTac |
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| serial EEPROM interface via the EExx pins. |
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| transfers Primary Host Strobe. Output data strobe (both edges). |
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/SSTOP |
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| The host may stop HSTROBE to pause output data transfers | S CS3# / strap | AF26 | O | Secondary Slave Chip Select. This signal corresponds to CS37X# |
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| UltraDMA Mode: SecondaryConfidentialStop. Stop transfer: Asserted by the |
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| on the secondary IDE connector. Strap information is | ||
/SHDMARDY |
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| UltraDMA Mode: Secondary Host DMA Ready. Input flow |
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| communicated to the north bridge via VD[7]. |
/SHSTROBE |
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| control. The host mayassert HDMARDY to pause input transfers | W24, | O | Primary Disk Address. PDA[2:0] are used to indicate which byte | |
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| Host Strobe B. Output strobe (both edges). The host may s op |
| V25, |
| in either the ATA command block or control block is being |
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| HSTROBE to pause output data transfers | W23 |
| accessed. | |
PDIOW# | Y25 | O | EIDE Mode: Primary Device I/O Write. Device write strobe | AE24, | O | Secondary Disk Address. SDA[2:0] are used to indicate which | |
/PSTOP |
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| UltraDMA Mode: Primary Stop. Stop transfer: Ass rt d by the |
| AC22, |
| byte in either the ATA command block or control block is being |
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| host prior to initiation of |
| AF24 |
| accessed. Strap information is communicated to the north bridge via |
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| an UltraDMA burst; negated by the host be ore data is transferred in |
| (see pin | IO | VD[6:4]. |
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| an UltraDMA burst. Assertion of STOP by the host during or after | Primary Disk Data. | |||
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| data transfer in UltraDMA m sig als the termination of the |
| list) |
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| burst. | (see pin | IO | Secondary Disk Data. | |
SDIOW# | AE23 | O | EIDE Mode: Secondary Device I/O Write. Device write strobe |
| list) |
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| host prior to initiation of an UltraDMA burst; negated by the host |
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| before data is transferred in an UltraDMA burst. Assertion of STOP |
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| by the host during or after data transfer in UltraDMA mode signals |
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| the termination of the burst. | Serial IRQ |
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PDDRQ | Y23 | I | Primary Device DMA Request. Primary channel DMA request | Signal Name | Pin # | I/O Signal Description | |
SDDRQ | AD17 | I | Secondary Device DMA Request. Secondary channel DMA | SERIRQ | AD9 | I | Serial IRQ. This pin has an internal |
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| request |
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