MiTAC 8399 5.2 VIA K8N800 North Bridge(3)

8399 N/B Maintenance

5.2 VIA K8N800 North Bridge(3)

V-Link Interface

Signal Name	Pin #	I/O
VAD7,	AF25	IO
VAD6,	AD24	IO
VAD5,	AF20	IO
VAD4,	AE19	IO
VAD3,	AE24	IO
VAD2,	AF24	IO
VAD1,	AD21	IO
VAD0	AD20	IO
VPAR	AF19	IO
VBE#	AE21	IO
UPCMD	AF26	I
UPSTB	AE23	I
UPSTB#	AF23	I
DNCMD	AD23	O
DNSTB	AF22	O
DNSTB#	AD22	O

SMB / I 2 C Interface

Signal Name	Pin #	I/O
SBPLCLK	/ AC10	I/O
GIRDY
SBPLDAT	/ AF11	I/O
GC#BE1
SBDDCCLK	/ Y1	I/O
GREQ
SBDDCDAT	/ AA3	I/O
GGNT	C2, P2	IO
SPCLK[2:1]
SPDAT[2:1]	C1, P1	IO

Dedicated Digital Video Port 0 (DVP0) – TMDS Interface

Signal Description					Signal Name		Pin #	I/O	Signal Description
Address / Data Bus. Also used to pass strap information from					DVP0D11/ TVD11		M1	O	Digital Video Port 0 Data. Default output drive is 8 mA. 16
the South Bridge to the North Bridge (the actual straps are on					DVP0D10/ TVD10		M3		mA may be selected via SR3D[6]=1.
the indicated South Bridge pin and that information is passed to					DVP0D9 / TVD9		M2
the North Bridge at reset time via the VAD pins).					DVP0D8 / TVD8		L1		NOTE: DVP0D[6:0] are also used for power-up reset straps
					DVP0D7 / TVD7		M4		for the embedded graphics controller. Check the Strap Pin
					DVP0D6 / TVD6		L3		able for details.
					DVP0D5 / TVD5		L2
					DVP0D4 / TVD4		K1
Parity.					DVP0D3 / TVD3		L4
Byte Enable.					DVP0D2 / TVD2		K3
					DVP0D1 / TVD1		K2
Command from Client (South Bridge) to Host (North
					DVP0D0 / TVD0		J1
Bridge).					DVP0HS / TVHS		N4	O	Digital Video Port 0 Horizontal Sync. Internally pulled
Strobe from Client to Host.			Secret						down.
Complement Strobe from Client to Host.							N3	O	Digital Video Port 0 Vertical Sync. Internally pulled down.
					DVP0VS / TVVS
Command from Host (North Bridge) to Client (South					VP0DE / TVDE		N1	O	Digital Video Port 0 Data Enable. Internally pulled down.
Bridge).				DocumentVP0DET / TVCLKR P4 I Digital Video Port 0 Display Detect. If VGA register
Strobe from Host to Client.									3C5.12[5]=0, 3C5.1A[5] will read 1 if display is connected.
Complement Strobe from Host to Client.									Tie to GND if not used.
		MiTac
	Confidential				DVP0CLK / TVCLK		P3	O	Digital Video Port 0 Clock. Internally pulled down.
					The terminology ie3C5.nnlg above refers to the VGA iGSequencerl. registers at I/O port 3C5 index
					“nn”
Signal Description
I 2 C Serial Bus Clock r Pa el (Muxed on AGP Bus Pins).					CRT Interface
I 2 C Serial Bus Data for Panel (Muxed on AGP Bus Pins).					Signal Name	Pin #		I/O	Signal Description
					AR	B3		AO Analog Red. Red output to CRT monitor.
I 2 C Serial Bus Clock for CRT DDC (Muxed on AGP Bus					AG	A3		AO Analog Green. Green output to CRT monitor.
					AB	A2		AO Analog Blue. Blue output to CRT monitor.
Pins).
					RSET	C4		AI CRT Output Reference Resistor. Tie to GNDRGB through an
I 2 C Serial Bus Data for CRT DDC (Muxed on AGP Bus
									external 90.9 ±1% resistor to
Pins).
									control the "RGB" RAMDAC full-scale current.
Serial Port (SMB/I 2 C) Clocks. Clocks for serial data transfer.
					HSYNC	A1		O Horizontal Sync. Digital output to CRT monitor.
SPCLK1 is typically used for I 2 C communications. SPCLK2
					VSYNC	B1		O Vertical Sync. Digital output to CRT monitor.
is typically used for CRT Display DDC communications.
Serial Port (SMB/I 2 C) Data. Data signals for serial data
transfer. SPDAT1 is typically used for I 2 C communications.
SPDAT2 is typically used for CRT Display DDC
communications.									75