CPU Speed Control Interface
Signal Name Pin # I/O Signal Description

8399 N/B Maintenance

5.3 VIA VT8235CD South Bridge(2)

Advanced Programmable Interrupt Controller (APIC) Interface

PCI Bus Interface

Signal Name Pin # I/O Signal Description

Signal Name Pin # I/O Signal Description

APICD1

T23

O

APICD0

R25

O

APICCLK

U23

I

VRDSLP

/ AB9

OD

GPI29/ GPO29

 

 

 

GHI# / GPI22/

R22

OD

GPO22

 

 

 

DPSLP#

/

P21

OD

GPI23/ GPO23

 

 

 

CPUMISS

/

Y1

I

GPI17

 

 

 

AGPBZ# / GPI6 AD10 I

Internal APIC Data 1. Function 0 Rx58[6] = 1

 

 

AD[31:0]

(see

IO

Address / Data Bus. Multiplexed address and data. The address

Internal APIC Data 0. Function 0 Rx58[6] = 1

 

 

 

pinlist)

 

is driven with FRAME#assertion and data is driven or received

 

 

 

 

 

in following cycles.

APIC Clock.

 

 

 

 

 

 

 

 

 

CBE[3:0]#

M3, L4, IO

Command / Byte Enable. The command is driven with

 

 

 

 

 

 

 

 

 

C1, E2

 

FRAME# assertion. Byteenables corresponding to supplied or

 

 

 

 

 

 

 

requested data are driven on following clocks.

 

 

 

 

DEVSEL#

H2

IO

Device Select. The VT8235 Version CE asserts this signal to

 

 

 

 

 

 

 

claim PCI transactions

 

 

 

 

 

 

 

through positive or subtractive decoding. As an input,

 

 

 

 

 

 

 

DEVSEL# indicates the response

 

 

 

 

 

 

 

to a VT8235 Version CE-initiated transaction and is also

 

 

 

 

 

 

 

sampled when decoding whether

Voltage Regulator Deep Sleep. Connected to the CPU voltage

 

 

 

 

 

to subtractively decode the cycle.

 

 

FRAME#

J1

IO

Frame. Assertion indicates the address phase of a PCI transfer.

regulator. High selectsthe proper voltage for deep sleep mode.

 

 

This pin performs the VRDPSLP function if

Secret

 

 

Negation indicates that

Function 0 RxE5[3] = 0.

 

 

 

 

 

 

one more data transfer is desired by the cycle initiator.

CPU Speed Select. Connected to the CPU voltage regulator,

 

 

IR Y#

J2

IO

Initiator Ready. Asserted when the initiator is ready for data

used to select high speed (L) or low speed (H). h s pin

 

Documenttransfer.

performs the GHI# function if Function 0 RxE5[3] = 0.

 

 

TRDY#

H1

IO

Target Ready. Asserted when the target is ready for data

CPU Deep Sleep. This pin performs the DPSLP# function

 

 

 

 

 

transfer.

Device 17 Function 0RxE5[3]=0.

MiTac

 

STOP#

K4

IO

Stop. Asserted by the target to request the master to stop the

CPU Missing. Used to detect the physical pr s nce of the CPU

 

 

 

 

 

current transaction.

chip in its socket. High

 

 

 

SERR#

C2

I

System Error. SERR# can be pulsed active by any PCI device

indicates no CPU present. Connect to the CPUMISS pin of the

 

 

 

 

 

that detects a system error

CPU socket. The state of

 

 

 

 

 

 

condition. Upon sampling SERR# active, the VT8235 Version

this pin may be read in the SMBus 2 registers. This pin may be

 

 

 

 

 

CE can be programmed to

used as CPUMISS and

 

 

 

 

 

 

generate an NMI to the CPU.

GPI17 at the same time.

 

 

 

PERR#

C3

_

Parity Error. PERR#, sustained tri-state, is only for the

AGP Busy. Low indicates that an AGP master cycle is in

 

 

 

 

 

reporting of data parity errors

progress (CPU speed transitions

 

 

 

 

 

 

during all PCI transactions except for a Special Cycle.

Confidential

PAR

F4

IO

Parity. A single parity bit is provided over AD[31:0] and

will be postponed if this input is asserted low). Connected to the

 

AGP Bus AGPBZ# pin.

 

 

 

 

 

 

C/BE[3:0]#.

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