8399 N/B Maintenance
5.3 VIA VT8235CD South Bridge(3)PCI Bus Interface (Continued) | LAN Controller - Media Independent Interface (MII) |
Signal Name Pin # I/O Signal Description | Signal Name Pin # I/O PU Signal Description |
INTA# | A4 | I |
INTB# | B4 |
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INTC# | B5 |
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INTD# | C4 |
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INTE# / GPI12, / | D4 |
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GPO12, |
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INTF# / GPI13, / | E4 |
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GPO13, |
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INTG# / GPI14, / A3 |
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GPO14, |
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INTH# / GPI15, / B3 |
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GPO15 |
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REQ5# / GPI7, | R3 | I |
REQ4#, | P3 |
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REQ3#, | D5 |
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REQ2#, | C5 |
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REQ1#, | B6 |
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REQ0# | A5 |
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GNT5# / GPO7, | R2 | O |
GNT4#, | R4 |
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GNT3#, | E5 |
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GNT2#, | C6 |
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GNT1#, | D6 |
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GNT0# | A6 |
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PCIRST# | R1 | O |
PCICLK | R23 | I |
PCKRUN# | AB7 | IO |
PCI Interrupt Request. The INTA# through INTD# pins are |
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| MCOL | B11 | I | PD | ||||
typically connected to thePCI bus |
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| MCRS | A11 | I | PD | ||||
table below. |
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Function 0 Rx5B[1] = 1. BIOS settings must match the physical |
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connection method. |
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| MDCK | A7 | O | PD | |
| INTA# | INTB# | INTC# | INTD# |
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PCI Slot 1 | INTA# | NTB# | INTC# | INTD# |
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PCI Slot 2 | INTB# | INTC# | INTD# | INTE# |
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| MDIO | B7 | IO | PD |
PCI Slot 3 | INTC# | INTD# | INTE# | INTF# |
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PCI Slot 4 | INTD# | INTE# | INTF# | INTG# |
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PCI Slot 5 | INTE# | INTF# | INTG# | INTH# |
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| MRXCLK | C9 | I | PD |
PCI Slot 6 | INTF# | INTG# | INTH# | INTA# |
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PCI Request. These signals connect to the VT8235 Version CE |
| C7, A8, | I | PD | ||||||
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from each PCI slot (oreach PCI master) to request the PCI bus. | Secret | B8, C8 |
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To use pin R3 as REQ5#, Function 0 RxE4 mustbe set to 1 |
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| MRXDV | D8 | I | PD | ||||
otherwise this pin will function as General Purpose Input 7. |
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| MRXERR | D10 | I | PD | |||||
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PCI Grant. These signals are driven by the VT8235 Vers on |
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| MTXCLK | C10 | I | PD | ||||
CE to grant PCI access to aspecific PCI master. To use pin R2 |
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as GNT5#, Function 0 RxE4 must be set to 1otherwise this pin |
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will function as General Purpose Output 7. |
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| A9, B9, | O | PD | |||||
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| B10, |
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PCI Reset. This signal is used to reset dev ces attached to the |
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PCI bus. |
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| MTXENA | C11 | O | PD |
PCI Clock. This signal pr vides timi g for all transactions |
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the PCI Bus. |
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| MIIVCC | D9, E9, | Power |
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PCI Bus Clock Run. This signal indicates whether the PCI |
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clock is or will be stoppedConfidential |
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(high) or running (low). The VT8235 Version CE drives this |
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signal low when the PCI |
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| MIIVCC25 | D12, | Power |
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clock is running (default on reset) and releases it when it stops |
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the PCI clock. External |
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| RAMVCC | E7 | Power |
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devices may assert this signal low to request that the PCI clock |
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| RAMGND | E6 | Power |
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be restarted or prevent it
from stopping. Connect this pin to ground using a 100 §Ù resistor if the function is not
used. Refer to the ihPCI Mobile Design Guidelo and applicable VIA North Bridge Design
Guide (KT400A, CLE266, or P4X400) for more details.
MII Collision Detect. From the external PHY.
MII Carrier Sense. Asserted by the external PHY when the media is
active.
MII Management Data Clock. Sent to the external PHY as a timing
reference for MDIO
MII Management Data I/O. Read from the MDI bit or written to the
MDO bit.
MII Receive Clock. 2.5 or 25 MHz clock recovered by the PHY.
MII Receive Data. Parallel receive data lines driven by the external
PHY synchronous with MRXCLK.
MII Receive Data Valid.
MII Receive Error. Asserted by the PHY when it detects a data
decoding error.
MII Transmit Clock. Always active 2.5 or 25 MHz clock supplied by
the PHY.
MII Transmit Data. Parallel transmit data lines synchronized to
MTXCLK.
MII Transmit Enable. Signals that transmit is active from the MII
port to the PHY.
MII Interface Power. 3.3V ±5%.
MII Suspend Power. 2.5V ±5%.
Power For Internal LAN RAM. 2.5V ±5%.
Ground For Internal LAN RAM.
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