8399 N/B Maintenance

5.3 VIA VT8235CD South Bridge(3)

PCI Bus Interface (Continued)

LAN Controller - Media Independent Interface (MII)

Signal Name Pin # I/O Signal Description

Signal Name Pin # I/O PU Signal Description

INTA#

A4

I

INTB#

B4

 

INTC#

B5

 

INTD#

C4

 

INTE# / GPI12, /

D4

 

GPO12,

 

 

INTF# / GPI13, /

E4

 

GPO13,

 

 

INTG# / GPI14, / A3

 

GPO14,

 

 

INTH# / GPI15, / B3

 

GPO15

 

 

REQ5# / GPI7,

R3

I

REQ4#,

P3

 

REQ3#,

D5

 

REQ2#,

C5

 

REQ1#,

B6

 

REQ0#

A5

 

GNT5# / GPO7,

R2

O

GNT4#,

R4

 

GNT3#,

E5

 

GNT2#,

C6

 

GNT1#,

D6

 

GNT0#

A6

 

PCIRST#

R1

O

PCICLK

R23

I

PCKRUN#

AB7

IO

PCI Interrupt Request. The INTA# through INTD# pins are

 

 

MCOL

B11

I

PD

typically connected to thePCI bus INTA#-INTD# pins per the

 

 

MCRS

A11

I

PD

table below. INTE-H# are enabled by setting Device17,

 

 

 

 

 

 

 

 

Function 0 Rx5B[1] = 1. BIOS settings must match the physical

 

 

 

 

 

connection method.

 

 

 

 

 

MDCK

A7

O

PD

 

INTA#

INTB#

INTC#

INTD#

 

 

 

 

 

 

 

 

 

PCI Slot 1

INTA#

NTB#

INTC#

INTD#

 

 

 

 

 

 

PCI Slot 2

INTB#

INTC#

INTD#

INTE#

 

 

MDIO

B7

IO

PD

PCI Slot 3

INTC#

INTD#

INTE#

INTF#

 

 

 

 

 

 

 

 

PCI Slot 4

INTD#

INTE#

INTF#

INTG#

 

 

 

 

 

 

PCI Slot 5

INTE#

INTF#

INTG#

INTH#

 

 

MRXCLK

C9

I

PD

PCI Slot 6

INTF#

INTG#

INTH#

INTA#

 

 

 

 

 

 

 

 

PCI Request. These signals connect to the VT8235 Version CE

 

MRXD[3-0]

C7, A8,

I

PD

 

 

 

 

 

from each PCI slot (oreach PCI master) to request the PCI bus.

Secret

B8, C8

 

 

To use pin R3 as REQ5#, Function 0 RxE4 mustbe set to 1

 

 

MRXDV

D8

I

PD

otherwise this pin will function as General Purpose Input 7.

 

 

 

 

MRXERR

D10

I

PD

 

 

 

 

 

 

 

 

 

 

 

 

 

Document

PCI Grant. These signals are driven by the VT8235 Vers on

 

 

MTXCLK

C10

I

PD

CE to grant PCI access to aspecific PCI master. To use pin R2

 

 

 

 

 

MiTac

 

 

 

 

 

as GNT5#, Function 0 RxE4 must be set to 1otherwise this pin

 

 

 

 

 

 

will function as General Purpose Output 7.

 

 

MTXD[3-0]

A9, B9,

O

PD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

B10,

 

 

PCI Reset. This signal is used to reset dev ces attached to the

 

 

 

A10

 

 

PCI bus.

 

 

 

 

 

 

MTXENA

C11

O

PD

PCI Clock. This signal pr vides timi g for all transactions

 

 

 

 

 

 

the PCI Bus.

 

 

 

 

 

MIIVCC

D9, E9,

Power

 

PCI Bus Clock Run. This signal indicates whether the PCI

 

 

 

clock is or will be stoppedConfidential

 

E10,

 

 

(high) or running (low). The VT8235 Version CE drives this

 

 

 

E11

 

 

signal low when the PCI

 

 

 

 

MIIVCC25

D12,

Power

 

clock is running (default on reset) and releases it when it stops

 

 

 

E12

 

 

the PCI clock. External

 

 

 

 

RAMVCC

E7

Power

 

devices may assert this signal low to request that the PCI clock

 

 

RAMGND

E6

Power

 

be restarted or prevent it

from stopping. Connect this pin to ground using a 100 §Ù resistor if the function is not

used. Refer to the ihPCI Mobile Design Guidelo and applicable VIA North Bridge Design

Guide (KT400A, CLE266, or P4X400) for more details.

MII Collision Detect. From the external PHY.

MII Carrier Sense. Asserted by the external PHY when the media is

active.

MII Management Data Clock. Sent to the external PHY as a timing

reference for MDIO

MII Management Data I/O. Read from the MDI bit or written to the

MDO bit.

MII Receive Clock. 2.5 or 25 MHz clock recovered by the PHY.

MII Receive Data. Parallel receive data lines driven by the external

PHY synchronous with MRXCLK.

MII Receive Data Valid.

MII Receive Error. Asserted by the PHY when it detects a data

decoding error.

MII Transmit Clock. Always active 2.5 or 25 MHz clock supplied by

the PHY.

MII Transmit Data. Parallel transmit data lines synchronized to

MTXCLK.

MII Transmit Enable. Signals that transmit is active from the MII

port to the PHY.

MII Interface Power. 3.3V ±5%.

MII Suspend Power. 2.5V ±5%.

Power For Internal LAN RAM. 2.5V ±5%.

Ground For Internal LAN RAM.

82