8399 N/B Maintenance
5.2 VIA K8N800 North Bridge(6)Clock, Reset, Power Control, General Purpose I/O, Interrupts and Test |
Signal Name
FP1HS
FP1VS
FP1DE
FP1DET
FP1CLK
FP1CLK#
Compensation
Signal Name
RPCOMP
RNCOMP
RTCOMP
VLPCOMP
AGPNCOMP
AGPPCOMP
AGP Name | Pin # | I/O | Signal Description |
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| Signal Name | Pin # | I/O | Signal Description | |||
GD9 | AD14 | O | Flat Panel Horizontal Sync. For port 1 in dual |
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| GCLK | A11 | I | AGP Clock. 66 MHz clock for AGP logic. | |||
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| DCLKI | D7 | I | Dot Clock (Pixel Clock) In. For spread spectrum. | ||
GPAR | AC16 | O | Flat Panel Vertical Sync. For port 1 in dual |
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| DCLKO | A7 | O | Dot Clock (Pixel Clock) Out. For spread spectrum. | |||||||
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| RESET# | AD25 | I | Reset. Input from the South Bridge chip. 3.3V tolerant input. | ||
GSERR | AC15 | O | Flat Panel Data Enable. For port 1 in dual |
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| When asserted, this signal resets the chip and sets all register | ||
GD8 | AF14 | I | Flat Panel Detect. For port 1 in dual |
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| bi s to the default value. The rising edge of this signal is used | |||
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| mode. |
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| to sample all | |
GD2 | AE18 | O | Flat Panel Clock. For port 1 in dual |
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| driven active to reset the K8 CPU. | |||
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| mode. |
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| PWROK | AE26 | I | Power OK. Driven by South Bridge PWROK output from the | |
GSTOP | AC12 | O | Flat Panel Clock Complement. For port 1 in |
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| power supply PWRGOOD input to the South Bridge. | |||
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| dual |
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| SUSST# | AD26 | I | Suspend Status. For implementation of the | ||
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| Secret |
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| disable. | |||
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| AC26 | I | Test In. This pin is used for testing and must be left | |||
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| TESTIN | |||
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| unconnected or tied high (4.7K §Ù to 2.5V) on all board |
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Pin # | I/O | Signal Description |
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| BISTIN | D3 | I | ||||
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| normal operation. | ||||||
D25 | AI | Host CPU |
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| DEBUG | AC17 | I | Debug. Reserved for test. Connect to ground for normal | ||||
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| resistor to GND. |
| MiTac |
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| operation. | |||
D26 | AI | Host CPU |
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| XIN | C6 | I | Reference Frequency In. 14.31818 MHz. | ||||
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| resistor to VCCHT. |
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| INTA# | E7 | O | PCI Interrupt Output A. Connect to the South Bridge. | |||
C26 | AI | Host CPU Compensation. Connect 100 §Ù 1% resistor to |
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| GPOUT | D2 | O | General Purpose Output. | ||||
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| VCCHT. |
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| GPO0 | N2 | O | General Purpose Output. | ||
AD19 | AI | sation. Connect 360 §Ù 1% |
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| resistor to ground. |
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W1 | AI | AGP |
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| resistor to VCCAGP. |
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V1 | AI | AGP |
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| resistor to GND. | Confidential |
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