8399 N/B Maintenance

5.2 VIA K8N800 North Bridge(6)

24-Bit / Dual 12-Bit Flat Panel Display Interface (Continued)

Clock, Reset, Power Control, General Purpose I/O, Interrupts and Test

Signal Name

FP1HS

FP1VS

FP1DE

FP1DET

FP1CLK

FP1CLK#

Compensation

Signal Name

RPCOMP

RNCOMP

RTCOMP

VLPCOMP

AGPNCOMP

AGPPCOMP

AGP Name

Pin #

I/O

Signal Description

 

 

Signal Name

Pin #

I/O

Signal Description

GD9

AD14

O

Flat Panel Horizontal Sync. For port 1 in dual

 

 

GCLK

A11

I

AGP Clock. 66 MHz clock for AGP logic.

 

 

 

 

12-bit mode.

 

 

 

DCLKI

D7

I

Dot Clock (Pixel Clock) In. For spread spectrum.

GPAR

AC16

O

Flat Panel Vertical Sync. For port 1 in dual

 

 

 

 

DCLKO

A7

O

Dot Clock (Pixel Clock) Out. For spread spectrum.

 

 

 

 

12-bit mode.

 

 

 

 

 

 

 

 

 

 

RESET#

AD25

I

Reset. Input from the South Bridge chip. 3.3V tolerant input.

GSERR

AC15

O

Flat Panel Data Enable. For port 1 in dual

 

 

 

 

 

 

12-bit mode.

 

 

 

 

 

 

When asserted, this signal resets the chip and sets all register

GD8

AF14

I

Flat Panel Detect. For port 1 in dual 12-bit

 

 

 

 

 

bi s to the default value. The rising edge of this signal is used

 

 

 

 

mode.

 

 

 

 

 

 

to sample all power-up strap options In addition, HTRST# is

GD2

AE18

O

Flat Panel Clock. For port 1 in dual 12-bit

 

 

 

 

 

driven active to reset the K8 CPU.

 

 

 

 

mode.

 

 

 

PWROK

AE26

I

Power OK. Driven by South Bridge PWROK output from the

GSTOP

AC12

O

Flat Panel Clock Complement. For port 1 in

 

 

 

 

 

power supply PWRGOOD input to the South Bridge.

 

 

 

 

dual 12-bit mode.

 

 

SUSST#

AD26

I

Suspend Status. For implementation of the

 

 

 

 

 

 

 

Secret

 

 

Suspend-to-DRAM feature. Connect to an external pull-up to

 

 

 

 

 

 

 

 

 

disable.

 

 

 

 

 

 

 

AC26

I

Test In. This pin is used for testing and must be left

 

 

 

 

 

 

 

 

 

TESTIN

 

 

 

 

 

 

 

 

 

 

 

 

unconnected or tied high (4.7K §Ù to 2.5V) on all board

 

 

 

 

 

 

 

 

 

 

 

 

designs.

 

 

 

 

 

 

 

 

Document

Pin #

I/O

Signal Description

 

 

 

BISTIN

D3

I

Built-In-Self-Test In. Reserved for test. Connect to GND for

 

 

 

 

 

 

normal operation.

D25

AI

Host CPU P-Channel Compensation. Connect 50 §Ù 1%

 

 

DEBUG

AC17

I

Debug. Reserved for test. Connect to ground for normal

 

 

resistor to GND.

 

MiTac

 

 

 

 

operation.

D26

AI

Host CPU N-Channel Compensation. Conn ct 50 §Ù 1%

 

 

XIN

C6

I

Reference Frequency In. 14.31818 MHz.

 

 

resistor to VCCHT.

 

 

 

INTA#

E7

O

PCI Interrupt Output A. Connect to the South Bridge.

C26

AI

Host CPU Compensation. Connect 100 §Ù 1% resistor to

 

 

GPOUT

D2

O

General Purpose Output.

 

 

VCCHT.

 

 

 

 

 

 

 

 

 

 

 

 

GPO0

N2

O

General Purpose Output.

AD19

AI

V-Link P-Channel Compe

sation. Connect 360 §Ù 1%

 

 

 

 

resistor to ground.

 

 

 

 

 

 

 

W1

AI

AGP N-Channel ompensation. Connect 60.4 §Ù 1%

 

 

 

 

 

 

 

 

resistor to VCCAGP.

 

 

 

 

 

 

 

V1

AI

AGP P-Channel Compensation. Connect 60.4 §Ù 1%

 

 

 

 

 

 

 

 

resistor to GND.

Confidential

 

 

 

 

 

 

 

 

 

 

 

 

 

 

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