8399 N/B Maintenance

￿AMD x86-64 Technology

￿AMD.s 64-bit x86 instruction set extensions

￿64-bit integer registers, 48-bit virtual addresses, 40-bit physical addresses

￿Eight new 64-bit integer registers (16 total)

￿Eight new 128-bit SSE/SSE2 registers (16 total)

￿Integrated Memory ControllerSecretDocument

￿Low-latency, high-bandwidth

￿72-bit DDR at 100, 133, 166 and 200MHz

￿HyperTransport. TechnologyMiTacto I/O Devices

￿Two 8-bit linksConfidentialeach support 1600 mega- r nsfers (MT) per second or 1.6 Gbytes/s in each direction

￿Can be configured as single 16-bit li k supporting 1600 MT/s or 3.2 Gbytes/s in each direction

￿64-Kbyte 2-way Associative ECC-Protected L1 Data Cache

￿Two 64-bit operati ns per cycle, 3-cycle latency

￿64-Kbyte 2-way Associative Parity-Protected L1 Instruction Cache

￿With advanced branch prediction

￿16-way Associative ECC-Protected L2 Cache

￿Exclusive cache architecture.storage in addition to L1 caches

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