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5.2 VIA K8N800 North Bridge(2)

AGP Bus Interface (Continued)

 

AGP Bus Interface (Continued)

Signal Name

Pin #

I/O

Signal Description

 

Signal Name

Pin #

I/O

Signal Description

AGP8XDT#

Y2

I

AGP 8x Transfer Mode Detect. Low indicates that the external

GSTOP(GSTOP

AC12

IO

Stop (PCI transactions only). Asserted by the target to request

 

 

 

graphics card can support 8x transfer mode

# for 4x)

 

 

the master to stop the current transaction. Interpreted as active

GRBF(GRBF#

AD6

I

Read Buffer Full. Indicates if the master (graphics controller)

 

 

 

high for AGP 8x.

for 4x)

 

 

is ready to accept previously requested low priority read data.

GREQ(GREQ#

Y1

I

Request. Master (graphics controller) request for use of the

 

 

 

When GRBF# is asserted, the North Bridge will not return low

for 4x)

 

 

AGP bus.

 

 

 

priority read data to the graphics controller.

GGNT(GGNT#

AA3

O

Grant. Permission is given to the master (graphics controller) to

GWBF(GWBF#

AC1

I

Write Buffer Full.

 

Document

 

for 4x)

 

 

use he AGP bus.

for 4x)

 

 

Side Band Address. Provides an additional bus to pass address

GSERR(GSERR

AC15

IO

AGP System Error.

GSBA[7:0]#

(see pin

I

# for 4x)

 

 

 

(GSBA[7:0] for

list)

 

and command information from the master (graphics controller)

Not : The AGP interface pins can be optionally configured as additional interfaces for connecting to

4x)

 

 

to the target (North Bridge). These pins are ignored until

exte nal display devices. For simplification of the AGP pin description tables above and on the next

GSBSTBF(GSB

 

 

enabled.

 

page, that ltiplexing is not shown here (see isAdditional 12C InterfaceslÓo, and display pin

AF1

I

Side Band Strobe. Driven by the master to provide timing for

description tables later in this document for more information).

STB for 4x),

AE1

 

GSBA[7:0]. 8x mode uses GSBSTBF (iBFirstlr strobe) and

Note: The AGP interface pins can be optionally configured as additional interfaces for connecting to

GSBSTBS(GSBS

 

 

 

MiTac

external display devices. For simplification of the AGP pin description tables above and on the next

 

 

GSBSTBS (iBSecondl) strobe). These signals are interpreted as

TB# for 4x)

 

 

GSBSTB & GSBSTB# for AGP4x.

 

page, that multiplexing is not shown here (see isAdditional I2C Interfacesll and display pin description

GST[2:0]

AB1

O

Status (AGP only). Provides information from the rbiter to

tables later in this document for more information).

 

AA1

 

101 Reserved. (arbiterConfidentialmust not issue, may be defined in the

 

 

 

 

 

master to indicate what it may do. Only val d wh le GGNT# is

Note: Separate system interrupts are not provided for AGP. The AGP connector provides interrupts via

 

AA2

 

asserted.

 

PCI bus INTA-B#.

 

 

 

 

 

 

000 Indicates that previously requested low priority read or

Note: A separate reset is not required for the AGP bus (RESET# resets both PCI and AGP buses)

 

 

 

flush data is being returned to the master (graphics

Note: Two mechanisms are provided by the AGP bus to enqueue master requests: GPIPE# (to send

 

 

 

controller).

 

addresses multiplexed on the AD lines) and the SBA port (to send addresses unmultiplexed). AGP

 

 

 

001 Indicates that previously requested high priority read data is

masters implement one or the other or select one at initialization time (they are not allowed to change

 

 

 

being returned to the master.

 

during runtime). Only one of the two will be used; the signals associated with the other will not be used.

 

 

 

010 Indicates that the master is to prov e low priority write

GRBF# has an internal pullup to maintain it in the de-asserted state in case it is not implemented on the

 

 

 

data for a previously enqueued wr te command.

master device. AGP 8x mode allows only SBA (GPIPE# isn™t used in 8x mode).

 

 

 

011 Indicates that the master is to provide high priority write

Note: AGP 8x signal levels are 0V and 0.8V. AGP 8x mode maintains most signals at a low level when

 

 

 

data for a previously enqueued write command.

inactive resulting in no current flow.

 

 

 

 

100 Reserved. (arbiter must t issue, may be defined in the

 

 

 

 

 

 

 

future).

 

 

 

 

 

future).

110 Reserved. (arbiter must not issue, may be defined in the future).

111 Indicates that the master (graphics controller) has been given permission to start a bus transaction. The master may enqueue AGP requests by asserting PIPE# or start a PCI transaction by asserting GFRM#. ST[2:0] are always outputs from the target (North Bridge logic) and inputs to the master (graphics controller).

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