8399 N/B Maintenance

5.3 VIA VT8235CD South Bridge(4)

Serial EEPROM Interface

 

 

 

Universal Serial Bus 2.0 Interface

Signal Name

Pin #

I/O

PU Signal Description

 

 

Signal Name

Pin #

I/O Signal Description

EECS#

D11

O

 

Serial EEPROM Chip Select.

 

 

USBP0+

E20

IO

USB 2.0 Port 0 Data +

EECK

C12

O

 

Serial EEPROM Clock.

 

 

USBP0Œ

D20

IO

USB 2.0 Port 0 Data Œ

EEDO

B12

I

 

Serial EEPROM Data Output. Connect to EEPROM Data

USBP1+

A20

IO

USB 2.0 Port 1 Data +

 

 

 

 

Out pin.

 

 

USBP1Œ

B20

IO

USB 2.0 Port 1 Data Œ

EEDI

A12

O

 

Serial EEPROM Data Input. Connect to EEPROM Data

 

 

 

USBP2+

E18

IO

USB 2.0

Port 2 Data +

 

 

 

 

In pin.

 

 

 

 

 

 

 

 

Document

 

 

 

 

 

 

 

 

USBP2Œ

D18

IO

USB 2.0 Port 2 Data Œ

 

 

 

 

 

 

Secret

A18

IO

USB 2.0

Port 3 Data +

 

 

 

 

 

 

 

USBP3+

Low Pin Count (LPC) Interface

 

 

USBP3Œ

B18

IO

USB 2.0 Port 3 Data Œ

 

 

USBP4+

D16

IO

USB 2.0

Port 4 Data +

Signal Name

Pin #

I/O

PU Signal Description

 

 

USBP4Œ

E16

IO

USB 2.0 Port 4 Data Œ

LFRM#

AF6

IO

 

LPC Frame.

MiTac

USBP5+

A16

IO

USB 2.0

Port 5 Data +

LREQ#

AE6

IO

 

 

 

LPC DMA / Bus Master Request.

 

USBP5Œ

B16

IO

USB 2.0 Port 5 Data Œ

LAD[3-0]

AD7,

IO

 

PU LPC Address / Data.

 

 

 

 

 

USBCLK

E23

I

USB 2.0

Clock. 48MHz clock input for the USB interface

 

AE7,

 

 

 

 

 

SMBDT1

IO SMB / I 2 C Channel 1ConfidentialData.

C26

er

USB 2.0

Port 0 Over Current Detect. Port 0 is disabled if low.

AB2

 

AF7,

 

 

 

 

 

USBOC0#

I

 

AD8

 

 

 

 

 

USBOC1#

D24

I

USB 2.0

Port 1 Over Current Detect. Port 1 is disabled if low.

Note: Connect the LPC interface LPCRST# (LPC Reset) signal to PCIRST#

 

USBOC2#

B26

I

USB 2.0

Port 2 Over Current Detect. Port 2 is disabled if low.

 

 

 

 

 

 

 

USBOC3#

C25

I

USB 2.0

Port 3 Over Current Detect. Port 3 is disabled if low.

 

 

 

 

 

 

 

USBOC4#

B24

I

USB 2.0

Port 4 Over Current Detect. Port 4 is disabled if low.

System Management Bus (SMB) Interface (I 2 C Bus)

 

 

USBOC5#

A24

I

USB 2.0

Port 5 Over Current Detect. Port 5 is disabled if low.

Signal Name

Pin #

I/O Signal Description

 

 

USBVCC

(see pin

Pow USB 2.0

Port Differential Output Interface Logic Voltage. 3.3V

SMBCK1

AC4

IO

SMB / I 2 C Channel 1 Cl ck.

 

 

 

list)

er

 

 

 

 

USBGND

(see pin

Pow USB 2.0

Port Differential Output Interface Logic Ground.

SMBCK2 /

AC3

IO

SMB / I 2 C Channel 2 ck. Rx95[2] = 0

 

 

 

list)

er

 

 

GPI27 / GPO27

 

 

 

 

 

 

VSUSUSB

C24

Pow USB 2.0 Suspend Power. 2.5V ±5%.

SMBDT2 /

AD1

IO SMB / I 2 C Channel 2 Data. Rx95[2] = 0

 

VCCUPLL

A23,

Pow USB 2.0 PLL Analog Voltage. 2.5V ±5%.

GPI26 / GPO26

 

 

 

 

 

 

 

B23

er

 

 

SMBALRT#

AB1

I SMB Alert. (enabled by System Management Bus I/O space

 

GNDUPLL

C23,

Pow USB 2.0 PLL Analog Ground.

 

 

 

Rx08[3] =

 

 

 

D23

er

 

 

1) When the chip is enabled to allow it, assertion generates an IRQ or

SMI interrupt or a power management resume event. Connect to a 10K

ohm pullup to VSUS33 if not used.

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