MiTAC 8399 5.1AMD Mobile Athlon 64(ClawHammer) Processor(1)

8399 N/B Maintenance

5.Pin Descriptions of Major Components

5.1AMD Mobile Athlon 64(ClawHammer) Processor(1)

DDR SDRAM Memory Interface Pins		DDR SDRAM Memory Interface Pins (Continued)
Signal Name	Type Description	Signal Name	Type Description

MEMCLK_H/L[7] MEMCLK_H/L[6] MEMCLK_H/L[5] MEMCLK_H/L[4] MEMCLK_H/L[3] MEMCLK_H/L[2] MEMCLK_H/L[1] MEMCLK_H/L[0]

MEMCKEA

MEMCKEB MEMDQS[17:0]

MEMDATA[63:0]

MEMCHECK[7:0] MEMCS_L[7:0]

MEMRASA_L MEMRASB_L

MEMCASA_L MEMCASB_L

MEMWEA_L

MEMWEB_L

MEMADDA[13:0]

MEMADDB[13:0]

O-IOD	Differential DDR SDRAM clock to the top of DIMM 0 for				MEMBANKA[1:0]	O-IOS	DRAM Bank Address. Two copies are provided to
	unbuffered DIMMs.1				MEMBANKB[1:0]		accommodate the loading of unbuffered DIMMs. During
O-IOD	Differential DDR SDRAM clock to the top of DIMM 1 for						precharges, activates, reads, and writes the two copies are
	unbuffered DIMMs.1						inverted from each other to minimize switching noise. The
O-IOD	Differential DDR SDRAM clock to the bottom of DIMM 0 for						signals are inverted only when the bus is used to carry address
	unbuffered DIMMs.1						information.1
O-IOD	Differential DDR SDRAM clock to the bottom of DIMM 1 for				MEMRESET L	O-IOS	DRAM Reset pin for Suspend-to-RAM power management
	unbuffered DIMMs.1						mode. This pin is required for registered DIMMs only.
O-IOD	Differential DDR SDRAM clock to DIMM 3 for registered				MEMVREF	VREF	DRAM Interface Voltage Reference 1
O-IOD	DIMMs.1				MEMZP	A	Compensation Resistor tied to VSS 1
	Differential DDRS DRAM clock to DIMM 2 for registered				MEMZN	A	Compensation Resistor tied to 2.5 V 1
	DIMMs.1
					Note: For connection details and proper resistor values, see the AMD Athlon™ 64 Processor
O-IOD	Differential DDR SDRAM clock to the middle of DIMM 1 for
	unbuffered DIMMs, or DIMM 1 for registered DIMMs.1				Motherboard Design Guide, order# 24665.
O-IOD	Differential DDR SDRAM clock to the middle of DIMM 0 for		Secret
				Document
	unbuffered DIMMs, or DIMM 0 for registered DIMMs.1
O-IOS	Clock Enables to DIMMs. Used to gate clocks for power
	management functionality.1
B-IOS	DRAM Data Strobes synchronous with E DATA and				HyperTransport™ Technology Pin Descriptions
	MEMCHECK during DRAM read and writes.1
B-IOS	DRAM Interface Data Bus	MiTac			Signal Name	Type	Description
B-IOS	DRAM Interface ECC Check Bits				L0_CLKIN_H/L[1:0]	I-HT	Link 0 Clock Input
O-IOS	DRAM Chip Selects 1				L0_CTLIN_H/L[1:0]	I-HT	Link 0 Control Input 2
O-IOS	DRAM Row Address Select. MEMRASA L and				L0_CADIN_H/L[15:0]	I-HT	Link 0 Command/Address/Data Input
	MEMRASB_L are functionally ide tical. Two copies are				L0_CLKOUT_H/L[1:0]	O-HT	Link 0 Clock Outputs
	provided to accommodate the	adi g of unbuffered DIMMs.1			L0_CTLOUT_H/L[1:0]	O-HT	Link 0 Control Output
O-IOS	DRAM Column Address Select. MEMCASA L and
					L0_CADOUT_H/L[15:0]	O-HT	Link 0 Command/Address/Data Outputs
	MEMCASB_L are functionally identical. Two copies are
O-IOS	provided to accommodateConfidentialthe loading of unbuffered DIMMs.1				L0_REF1	A	Compensation Resistor to VLDT 1
	DRAM Write Enable. MEMWEA_L and MEMWEB_L are				L0_REF0	A	Compensation Resistor to VSS 1
	functionally identical. Two copies are provided to accommodate
					Note: 1.These pins are used in an alternating fashion to compensate R TT by internal comparison to 3/4
	the loading of unbuffered DIMMs.1
O-IOS	DRAM Column/Row Address. Two copies are provided to				VLDT and 1/4 VLDTand compensate R ON by comparison to each other around 1/2 VLDT.
	accommodate the loading of unbuffered DIMMs. During				For proper resistor value, see theAMD Athlon™ 64 Processor Motherboard Design Guide, order#
	precharges, activates, reads, and writes, the two copies are				24665.
	inverted from each other (except A[10] which is used for				2.The unused L0_CTLIN_H/L[1] pins must be properly terminated such that the true pin is pulled
	auto-precharge) to minimize switching noise. The signals are				High and thecomplement is pulled Low. Refer to the AMD Athlon™ 64 Processor Motherboard
	inverted only when the bus is used to carry address				Design Guide, order# 24665, for details.

information.1

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