8399 N/B Maintenance
5.2 VIA K8N800 North Bridge(1)AGP Bus Interface
Signal Name | Pin # | I/O |
GD[31:0] | (see pin | IO |
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GC#BE[3:0] | AC7 | IO |
(GCBE[3:0]# for | AD11 |
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4x mode) | AF11 |
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| AD15 |
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GPAR | AC16 | IO |
GDBIH | / AC5 | IO |
GPIPE#GDBIL | AC4 |
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GADSTB0F(GA | AE15 | IO |
DSTB0 for 4x), |
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GADSTB0S(GA | AF15 |
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DSTB0# for 4x) |
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AGP Bus Interface (Continued)
Signal Description |
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| Signal Name | Pin # | I/O | Signal Description |
Address / Data Bus. Address is driven with GDS assertion for |
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| GADSTB1F(GA | AE7 | IO | Bus Strobe 1. Source synchronous strobes for GD[31:16] (i.e., | ||
| DSTB1 for 4x), |
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| the agent that is providing the data drives these signals). GDS1 | ||||
transfers. |
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| GADSTB1S(GA | AF7 |
| provides timing for 2x data transfer mode; GDS1 and GDS1# |
Command / Byte Enable. (Interpreted as GC/BE# for AGP |
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| DSTB1# for 4x) |
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| provide timing for 4x transfer mode. For 8x transfer mode, | ||
2x/4x and GC#/BE for 8x). For AGP cycles these pins provide |
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| GDS1 is interpreted as GDS1F (iSFirstle strobe) and GDS1# as | |||
command information (different commands than for PCI) driven |
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| GDS1S (iSSecondld strobe). | ||||
by the master (graphics controller) when requests are being |
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corresponding data bit group (GDBIH for GD[31:16] and |
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enqueued using GPIPE# (2x/4x only as GPIPE# isn™t used in |
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| GFRAME(GFR | AC9 | IO | Frame. Assertion indicates the address phase of a PCI transfer. | ||
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| Secret |
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| Negation indicates that one more data transfer is desired by the | ||
8x mode). These pins provide valid byte information during |
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| AME# for 4x) |
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AGP write transactions and are driven by the master. The target |
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| cycle initiator. Interpreted as active high for 8x. | ||
(this chip) drives these lines to io0000lt during the return of |
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| GIRDY(GIRDY | AC10 | IO | Initiator Ready. (Interpreted as active low for PCI/AGP2x/4x | ||
AGP read data. For PCI cycles, commands are driven with |
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| # for 4x) |
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| and high for AGP 8x). For AGP write cycles, the assertion of | ||
GFARME# assertion. Byte enables corresponding to supplied or |
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| this pin indicates that the master is ready to provide all | |||
requested data are driven on following clocks. |
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| write data for the current transaction. Once this pin is asserted, | ||
AGP Parity. A single parity bit is provided over GD[31:0] and |
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| the master is not allowed to insert wait states. For AGP read | ||
GC#BE[3:0]. | MiTac |
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| cycles, the assertion of this pin indicates that the master is ready | ||
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Dynamic Bus Inversion High / Low. AGP 8x transfer mode |
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| to transfer a subsequent block of read data. The master is never | ||
only. Driven by the source to indicate whether the |
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| allowed to insert a wait state during the initial block of a read | ||
agent that is providingConfidentialthe data drives these signals). GDS0 | VSEL# for 4x |
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| the North Bridge when a PCI initiator is attempting to access | ||||
GDBIL for GD[15:0]) needs to be inverted on the receiving end |
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| transfers. For PCI cycles, asserted when the initiator is ready | ||
(1 on GDBIx indicates that the corresponding data bit group |
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| for data transfer. | ||
should be inverted). Used to limit the number of simultaneously |
| GTRDY(GTRD | AC14 | IO | Target Ready. (Interpreted as active low for PCI/AGP2x/4x | |||
switching outputs to 8 for each |
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| Y# for 4x) |
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| and high for AGP 8x). For AGP cycles, indicates that the target | ||
Pipelined Request. Not used by AGP 8x. Ass rt d by the |
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| is ready to provide read data for the entire transaction (when | ||
master (external graphics controller) to in | icate that |
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| the transaction can complete within four clocks) or is ready to | ||
request is to be enqueued by the target (North Bridge). The |
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| transfer a (initial or subsequent) block of data when the transfer | ||
master enqueues one request each ris ng e | ge of GCLK while |
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| requires more than four clocks to complete. The target is | |||
GPIPE# is asserted. When GPIPE# is deasserted no new |
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| allowed to insert wait states after each block transfer for both | |||
requests are enqueued acr ss the AD bus. |
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| read and write transactions. For PCI cycles, asserted when the | ||
Note: See RxAE[1] for GPIPE# / GDBIH pin function |
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selection. |
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| target is ready for data transfer. |
Bus Strobe 0. Source synchronous strobes for GD[15:0] (the |
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| GDEVSEL(GDE AC11 | IO | Device Select (PCI transactions only). This signal is driven by | |||
provides timing for 2x data transfer mode; GDS0 and GDS0# |
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| mode) |
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| main memory. It is an input when the chip is acting as PCI | ||
provide timing for 4x mode. For 8x transfer mode, GDS0 is |
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| initiator. Not used for AGP cycles. Interpreted as active high for | ||
interpreted as GDS0F (i1Firstl. strobe) and GDS0# as GDS0S |
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| AGP 8x. | ||
(iSSecondl. strobe). |
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