8399 N/B Maintenance

5.2 VIA K8N800 North Bridge(7)

Integrated Graphics Power and Ground

Signal Name

Pin #

I/O

VCCDAC

B2

P

GNDDAC

C3, D4

P

VCCRGB

A4

P

GNDRGB

B4

P

VCCPLL1

D5

P

GNDPLL1

C5

P

VCCPLL2

A5

P

GNDPLL2

B5

P

VCCPLL3

A6

P

GNDPLL3

B6

P

Signal Description

 

 

DAC Voltage. 3.3V ±5% connected via ferrite bead for

 

 

isolation of digital switching noise.

 

 

DAC Ground. Connect to main ground plane.

 

 

Power for CRT RGB Outputs. 3.3V ±5% connected via

 

 

ferrite bead for isolation of digital switching noise

 

 

Connection point for RGB Load Resistors. Connect to main

 

ground plane via ferrite bead for isolation of digital switching

Secret

noise.

 

Power for Graphics Controller PLL1 (“E-Clock”). 1.5V

±5% connected via ferrite bead for isolation of digital

switching noise.

 

Ground for Graphics Controller PLL1 (“E-Clock”).

Connect to main ground plane via ferrite bead for isolation of

digital switching noise.

Power for Graphics Controller PLL2 (“D-Clock”). 1.5V

 

Document

±5% connected via ferrite bead for isolation of digit l

 

switching noise.

 

 

Ground for Graphics Controller PLL2 (“D-Clock”).

 

Connect to main ground plane via ferrite bead for isola ion of

 

 

digital switching noise.

 

 

Power for Graphics Controller PLL3MiTac(“LCD Clock”). 1.5V

 

±5% connected via ferrite bead for isolation of digital

 

 

switching noise.

 

 

 

Ground for Graphics Controller PLL3 (“LCD Clock”).

 

 

Connect to main ground plane via err te bead for isolation of

 

 

digital switching noise.

 

 

 

Confidential

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