Quatech INTERBUS S Organization of the in- and output data, Status byte has the following bits

Organization of the in- and output data:

The counter begins processing with pulses at the CLOCK input. The changes from 0 V to 24 V are counted.

The counter counts up, if the input U/D is set at 24 V. With an open circuit input or 0 V the counter counts backwards.

The two bottom contacts each include another output. These outputs are activated through bits in the control byte.

The control byte has the following bits:

Bit 7	Bit 6	Bit 5
0	x	Set Counter

Bit 4

Block Counter

Control Byte

Bit 3

Output value at output O2

Bit 2

Output value at output O1

Bit 1

x

Bit 0

x

The status byte has the following bits:

				Status Byte
Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2
x	x	Counter is	Counter is	actual signal at	actual signal
		set	blocked	O2	at O1

Bit 1

actual signal at input U/D

Bit 0

actual signal at input CLOCK

With the control and status-byte the following tasks are possible:

Set the counter: Put Bit 5 into the control byte. The counter with the 32 bit value is loaded into output bytes 0-3. As long as the bits are set, the counter can stop and information is stored. The ensuing data of the counter will be conveyed to the status byte.

Blocking the counter: Bit 4 is set into the control byte, then the count process is suppressed. Bit 4 in the status byte communicates the suppression of the counter.

Set the outputs: Bits 2 and 3 set the additional two outputs of the counter module.

The result of the counter is in binary.

Counter￿￿￿￿￿￿￿￿Module 750-404 3

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