Quatech INTERBUS S manual Status byte contains the information as listed below

The input Latch controls the overtaking of the actual counter value into the Latchregister. This input is activated by teh control bit EN_LATEXT („1“). EN_LACT has to be deactivated („0“). The first change from 0 V to 24 V at the Latch input takes the actual counter value into the Latchregister.

The control byte contains the information as listed below.

Control Byte Configuration

Bit 7	Bit 6	Bit 5
0	x	CFAST_M
0	x	Operation
		Mode

Bit 4

x

x

Bit 3

x

x

Bit 2

CNT_SET

Counter Set

Bit 1

EN_LATEXT

Release Latch

Bit 0

EN_LATC

Release Index Pulse

Please note Bit 7 is a reserved bit and must always be set to 0. It is responsible for register communication which is not decribed in this chapter.

Bit

CFAST_M

CNT_SET

EN_LATEXT

EN_LACT

Function

Fast mode operation. Only the counter module function will be operable. All other control bits will be ignored.

The counter module will be preset to a count value with a rising edge.

0=The external latch input is deactivated.

1=The module will latch in the counter data on the first rising edge. Other changes have no effect.

0=Latching data with the Index pulse is deactivated. 1=The Index pulse will latch in the counter data on the first rising edge. Other changes have no effect.

The status byte contains the information as listed below.

Status Byte Configuration

Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2
0	x	x	OVERFLOW	UNDERFLOW	CNTSET_ACC
0	x	x	Counter	Counter	Counter Set
			Overflow	Underflow	Acknowledge

Bit 1

LATEXT_ VAL

External Latch Ack.

Bit 0

LATC_

VAL

Latched Data Set

Bit

OVERFLOW

UNDERFLOW

CNTSET_ACC

LATEXT_VAL

LACT_VAL

Function

The Overflow bit will be set if the counter value rolls over from 65535 to

0.This bit will automatically be reset if the counter passes through more than one third of the count range, 21845 to 21846, or if an Underflow occurs.

The Underflow bit will be set if the counter value rolls back from 65535 to 0. This bit will automatically be reset if the counter passes through more than two thirds of the count range, 43690 to 43689, or if an Overflow occurs.

The Counter Set Acknowledge but is set when a valid counter value is preset to the module.

The Latch External Valid Acknowledge bit is set when a counter value is latched into the module via the Latch input.

The Latch Index Pulse Valid Acknowledge bit is set when a counter value is latched into the module via the Index pulse.

Quadrature￿￿￿￿￿￿￿￿Encoder 750-631 4

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