Functional description
The counter module acquires the time between one or more rising edges of the CLOCK input signal and calculates the frequency of the applied signal.
The calculation and process image update are initiated every 1st, every 4th or every 16th rising edge depending on the integration time selected via the CONTROL byte. The first detection of a rising edge starts the cyclic period measurement and cannot provide a valid frequency value. In this case the module will send 0xFFFFFFFFH for input information. The same input value is returned when a static high or static low signal is applied to the CLOCK input.
If there are no signal changes seen at the CLOCK input, the module can be forced to update the process image after defined parameterizable time spans. In this state the module will send the non valid value 0xFFFFFFFFH too.
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7 | 0D[LPXPGDWDKROGWLPHSDUDPHWHUL]DEOH |
Figure 2: Timing diagram for process data update sequence | |||||
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| 7 | 0D[LPXPGDWDKROGWLPHSDUDPHWHUL]DEOH |
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Figure 3: Timing diagram for process data update sequence (integration time = 4 periods)
CounterModule | 10 |
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