Hardware Information
Release 04/02
7-21
Panel PC 670 Computing Unit, Equipment Manual
Display port (LVDS), X400
TFT displays with an LVDS port can be connected to this port. 18-bit displays
having a resolution up to 1024x768 pixels can be connected. The permissible
display clock rate is 20 MHz to 66 MHz. The display is selected automatically
according to the code of the Display Select inputs. The display supply voltages
(3,3 V and 5 V) are connected as a function of the requirements for the connected
displays via the graphics controller. The maximum cable length is 50 cm at a
transfer rate of 455 MHz. Specific cable properties have to be taken into account
for differential cable pairs in accordance with the LVDS specification.
Pin
No. Short Name Meaning Input/Output
1 P5V_D_fused +5V (fused) Display VCC Output
2 P5V_D_fused +5V (fused) Display VCC Output
3 RXIN0–LVDS output signal bit 0 (-) Output
4 RXIN0+ LVDS output signal bit 0 (+) Output
5 P3V3_D_fused +3.3V (fused) display VCC Output
6 P3V3_D_fused +3.3V (fused) display VCC Output
7 RXIN1–LVDS output signal bit 1 (-) Output
8 RXIN1+ LVDS output signal bit 1 (+) Output
9 GND Chassis ground -
10 GND Chassis ground -
11 RXIN2–LVDS output signal bit 2 (-) Output
12 RXIN2+ LVDS output signal bit 2 (+) Output
13 GND Chassis ground -
14 GND Chassis ground -
15 RXCLKIN–LVDS clock signal (–) Output
16 RXCLKIN+ LVDS clock signal (+) Output
17 GND Chassis ground -
18 GND Chassis ground -
19 Reserved
20 Reserved