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TMS320C642X manual Users Guide, Literature Number SPRUEN0D March
Models:
TMS320C642X
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1.3Functional Block Diagram
Configure the Mode Register
Reset Considerations
2.4Signal Descriptions
2.15Power Management
1.2Features
2.6.4Using a Repeated START Condition
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TMS320C642x DSP
Inter-Integrated
Circuit (I2C) Peripheral
User's Guide
Literature Number: SPRUEN0D
March 2011
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Contents
Literature Number SPRUEN0D March
Users Guide
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SPRUEN0D - March
2011, Texas Instruments Incorporated
Preface
List of Figures
List of Tables
Preface
Read This First
About This Manual
Notational Conventions
Users Guide
Inter-IntegratedCircuit I2C Peripheral
1.2Features
1.2.1Features Not Supported
Figure 1. I2C Peripheral Block Diagram
1.3Functional Block Diagram
1.4Industry Standards Compliance Statement
2.1Bus Structure
2Peripheral Architecture
Figure 2. Multiple I2C Modules Connected
2.2Clock Generation
Figure 3. Clocking Diagram for the I2C Peripheral
2.3Clock Synchronization
2.4Signal Descriptions
2.4.1Input and Output Voltage Levels
2.4.2Data Validity
2.5START and STOP Conditions
Figure 5. Bit Transfer on the I2C-Bus
Figure 7. I2C Peripheral Data Transfer
2.6Serial Data Formats
2.6.17-BitAddressing Format
2.6.210-BitAddressing Format
2.6.4Using a Repeated START Condition
FDF = 0, XA = 1 in ICMDR
2.6.3Free Data Format
2.8Operating Modes
2.7Endianness Considerations
Table 1. Operating Modes of the I2C Peripheral
Table 2. Ways to Generate a NACK Bit
2.9NACK Bit Generation
Peripheral Architecture
NACK Bit Generation
2.10 Arbitration
2.11.1Software Reset Considerations
2.11 Reset Considerations
2.11.2Hardware Reset Considerations
2.12 Initialization
2.Place I2C in reset clear IRS = 0 in ICMDR
7.Configure the Mode Register
2.13 Interrupt Support
2.15Power Management
2.14 DMA Events Generated by the I2C Peripheral
2.13.1Interrupt Events and Requests
3Registers
2.16 Emulation Considerations
Table 4. Inter-IntegratedCircuit I2C Registers
Figure 13. I2C Own Address Register ICOAR
3.1I2C Own Address Register ICOAR
Figure 14. I2C Interrupt Mask Register ICIMR
3.2I2C Interrupt Mask Register ICIMR
Registers
Field
Figure 15. I2C Interrupt Status Register ICSTR
3.3I2C Interrupt Status Register ICSTR
Field
continued
Description
Inter-IntegratedCircuit I2C Peripheral
Value
Field
Description
Inter-IntegratedCircuit I2C Peripheral
3.4.1I2C Clock Low-TimeDivider Register ICCLKL
3.4I2C Clock Divider Registers ICCLKL and ICCLKH
3.4.2I2C Clock High-TimeDivider Register ICCLKH
Figure 18. I2C Data Count Register ICCNT
3.5I2C Data Count Register ICCNT
3.7I2C Slave Address Register ICSAR
3.6I2C Data Receive Register ICDRR
Figure 19. I2C Data Receive Register ICDRR
Figure 20. I2C Slave Address Register ICSAR
Figure 21. I2C Data Transmit Register ICDXR
3.8I2C Data Transmit Register ICDXR
Figure 22. I2C Mode Register ICMDR
3.9I2C Mode Register ICMDR
Value
Field
Description
Inter-IntegratedCircuit I2C Peripheral
Value
Field
Description
ICMDR Bit
I2C State
ICMDR Bit
Function of TRX Bit
Figure 24. I2C Interrupt Vector Register ICIVR
3.10 I2C Interrupt Vector Register ICIVR
Figure 25. I2C Extended Mode Register ICEMDR
3.11 I2C Extended Mode Register ICEMDR
Figure 26. I2C Prescaler Register ICPSC
3.12 I2C Prescaler Register ICPSC
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Table 22. Document Revision History
Appendix A Revision History
Reference Additions/Modifications/Deletions
Revision History
Products
IMPORTANT NOTICE
Applications
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