Users Guide | Texas Instruments TMS320C642X instruction

TMS320C642x DSP Inter-Integrated Circuit (I2C) Peripheral

User's Guide

Literature Number: SPRUEN0D

March 2011

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Texas Instruments TMS320C642X manual Users Guide

Contents

Users Guide Submit Documentation Feedback Appendix a Revision History List of Figures List of Tables Read This First Features Not Supported FeaturesPurpose of the Peripheral Industry Standards Compliance Statement Functional Block Diagram Multiple I2C Modules Connected Bus Structure Clock Generation Clocking Diagram for the I2C Peripheral Clock Synchronization Signal DescriptionsInput and Output Voltage Levels Data Validity Start and Stop Conditions 1 7-Bit Addressing Format Serial Data Formats 2 10-Bit Addressing Format Using a Repeated Start ConditionFree Data Format ACK Endianness Considerations Operating Mode DescriptionOperating Modes Operating Modes of the I2C Peripheral Ways to Generate a Nack Bit Nack Bit GenerationNack Bit Generation I2C Peripheral Condition Basic Optional Arbitration Arbitration Procedure Between Two Master-Transmitters Software Reset Considerations Reset ConsiderationsHardware Reset Considerations Initialization Configuring the I2C in Slave Receiver and Transmitter Mode Peripheral Architecture Interrupt Support Power ManagementDMA Events Generated by the I2C Peripheral Inter-Integrated Circuit I2C Registers Emulation ConsiderationsAcronym Register Description I2C Own Address Register Icoar Field Descriptions I2C Own Address Register IcoarOaddr Bit Field Value Description I2C Interrupt Mask Register Icimr Field Descriptions I2C Interrupt Mask Register IcimrSCD Icxrdy Icrrdy Ardy Nack AAS I2C Interrupt Status Register Icstr Field Descriptions I2C Interrupt Status Register IcstrSdir Nacksnt Rsfull Xsmt Sdir AD0 Bit Field An acknowledge bit ACK has been sent by the receiver 1 I2C Clock Low-Time Divider Register Icclkl I2C Clock Divider Registers Icclkl and Icclkh2 I2C Clock High-Time Divider Register Icclkh Iccl I2C Data Count Register Iccnt Field Descriptions I2C Data Count Register IccntIcdc I2C Slave Address Register Icsar I2C Data Receive Register IcdrrI2C Data Receive Register Icdrr Field Descriptions I2C Slave Address Register Icsar Field Descriptions I2C Data Transmit Register Icdxr Field Descriptions I2C Data Transmit Register Icdxr I2C Mode Register Icmdr Field Descriptions I2C Mode Register Icmdr RM bit is dont care Bus Activity Description Icmdr Bit I2C State Function of TRX Bit How the MST and FDF Bits Affect the Role of TRX Bit I2C Interrupt Vector Register Icivr Field Descriptions 10 I2C Interrupt Vector Register IcivrIntcode I2C Extended Mode Register Icemdr Field Descriptions 11 I2C Extended Mode Register IcemdrIgnack BCM R/W-0 R/W-1 Ignack I2C Prescaler Register Icpsc Field Descriptions 12 I2C Prescaler Register IcpscIpsc 14 I2C Peripheral Identification Register ICPID2 13 I2C Peripheral Identification Register ICPID1Type I2C Reference Additions/Modifications/Deletions Document Revision History DSP Products ApplicationsRfid TI E2E Community Home