Texas Instruments TMS320C642X manual 3.8I2C Data Transmit Register ICDXR

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3.8I2C Data Transmit Register (ICDXR)

The CPU or EDMA writes transmit data to the I2C data transmit register (ICDXR). The ICDXR can accept a data value of up to 8 bits. When writing a data value with fewer than 8 bits, the written data must be right-aligned in the D bits. The number of data bits is selected by the bit count bits (BC) of ICMDR. Once data is written to ICDXR, the I2C copies the contents of ICDXR into the I2C transmit shift register (ICXSR). The ICXSR shifts out the transmit data from the SDA pin. The CPU and the EDMA controller cannot access ICXSR.

The I2C data transmit register (ICDXR) is shown in Figure 21 and described in Table 13.

Figure 21. I2C Data Transmit Register (ICDXR)

31			16
	Reserved
		R-0
15	8	7	0
	Reserved		D
	R-0		R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

Table 13. I2C Data Transmit Register (ICDXR) Field Descriptions

Bit	Field	Value	Description
31-8	Reserved	0	These reserved bit locations are always read as zeros. A value written to this field has no effect.
7-0	D	0-FFh	Transmit data.

SPRUEN0D –March 2011	Inter-Integrated Circuit (I2C) Peripheral	31
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