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| Table 7. I2C Interrupt Status Register (ICSTR) Field Descriptions | (continued) | ||
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| Field | Value | Description |
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10 |
| XSMT |
| Transmit shift register empty bit. XSMT indicates that the transmitter has experienced underflow. | |
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| Underflow occurs when the transmit shift register (ICXSR) is empty but the data transmit register | |
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| (ICDXR) has not been loaded since the last | |
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| transfer will not occur until new data is in ICDXR. If new data is not transferred in time, the previous | |
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| data may be |
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| 0 | Underflow is detected. |
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| 1 | No underflow is detected. XSMT is set by one of the following events: |
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| • Data is written to ICDXR. |
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| • The I2C is reset (either when 0 is written to the IRS bit of ICMDR or when the processor is reset). | |
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9 |
| AAS |
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| 0 | The AAS bit has been cleared by a repeated START condition or by a STOP condition. | |
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| 1 | AAS is set by one of the following events: |
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| • I2C has recognized its own slave address or an address of all zeros (general call). | |
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| • The first data word has been received in the free data format (FDF = 1 in ICMDR). | |
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8 |
| AD0 |
| Address 0 bit. |
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| 0 | AD0 has been cleared by a START or STOP condition. |
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| 1 | An address of all zeros (general call) is detected. |
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| Reserved | 0 | These reserved bit locations are always read as zeros. A value written to this field has no effect. | ||
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5 |
| SCD |
| Stop condition detected bit. SCD indicates when a STOP condition has been detected on the I2C bus. | |
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| The STOP condition could be generated by the I2C or by another I2C device connected to the bus. | |
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| 0 | No STOP condition has been detected. SCD is cleared by one of the following events: | |
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| • By reading the INTCODE bits in ICIVR as 110b. |
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| • SCD is manually cleared. To clear this bit, write a 1 to it. |
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| 1 | A STOP condition has been detected. |
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4 |
| ICXRDY |
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| to accept new data because the previous data has been copied from ICDXR to the transmit shift | |
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| register (ICXSR). The CPU can poll ICXRDY or use the XRDY interrupt request. | |
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| 0 | ICDXR is not ready. ICXRDY is cleared by one of the following events: |
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| • Data is written to ICDXR. |
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| • ICXRDY is manually cleared. To clear this bit, write a 1 to it. |
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| 1 | ICDXR is ready. Data has been copied from ICDXR to ICXSR. ICXRDY is forced to 1 when the I2C is | |
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| reset. |
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3 |
| ICRRDY |
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| to be read because data has been copied from the receive shift register (ICRSR) to ICDRR. The CPU | |
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| can poll ICRRDY or use the RRDY interrupt request. |
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| 0 | ICDRR is not ready. ICRRDY is cleared by one of the following events: | |
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| • ICDRR is read. |
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| • ICRRDY is manually cleared. To clear this bit, write a 1 to it. |
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| • The I2C is reset (either when 0 is written to the IRS bit of ICMDR or when the processor is reset). | |
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| 1 | ICDRR is ready. Data has been copied from ICRSR to ICDRR. |
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2 |
| ARDY |
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| indicates that the I2C registers are ready to be accessed because the previously programmed address, | |
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| data, and command values have been used. The CPU can poll ARDY or use the ARDY interrupt | |
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| request. |
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| 0 | The registers are not ready to be accessed. ARDY is cleared by one of the following events: | |
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| • The I2C starts using the current register contents. |
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| • ARDY is manually cleared. To clear this bit, write a 1 to it. |
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| • The I2C is reset (either when 0 is written to the IRS bit of ICMDR or when the processor is reset). | |
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| 1 | The registers are ready to be accessed. This bit is set after the slave address appears on the I2C bus. | |
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| • In the nonrepeat mode (RM = 0 in ICMDR): If STP = 0 in ICMDR, ARDY is set when the internal data | |
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| counter counts down to 0. If STP = 1, ARDY is not affected (instead, the I2C generates a STOP | |
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| condition when the counter reaches 0). |
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| • In the repeat mode (RM = 1): ARDY is set at the end of each data word transmitted from ICDXR. | |
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26 | SPRUEN0D | ||||
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