Reset Considerations | Texas Instruments TMS320C642X specs

Peripheral Architecture

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2.11 Reset Considerations

The I2C peripheral has two reset sources: software reset and hardware reset.

2.11.1Software Reset Considerations

To reset the I2C peripheral, write 0 to the I2C reset (IRS) bit in the I2C mode register (ICMDR). All status bits in the I2C interrupt status register (ICSTR) are forced to their default values, and the I2C peripheral remains disabled until IRS is changed to 1. The SDA and SCL pins are in the high-impedance state.

NOTE: If the IRS bit is cleared to 0 during a transfer, this can cause the I2C bus to hang (SDA and SCL are in the high-impedance state).

2.11.2Hardware Reset Considerations

When a hardware reset occurs, all the registers of the I2C peripheral are set to their default values and the I2C peripheral remains disabled until the I2C reset (IRS) bit in the I2C mode register (ICMDR) is changed to 1.

NOTE: The IRS bit must be cleared to 0 while you configure/reconfigure the I2C peripheral.

Forcing IRS to 0 can be used to save power and to clear error conditions.

2.12 Initialization

Proper I2C initialization is required prior to starting communication with other I2C device(s). Unless a fully fledged driver is in place, you need to determine the required I2C configuration needed (for example, Master Receiver, etc.) and configure the I2C controller with the desired settings. Enabling the I2C clock should be the first task. Then the I2C controller is placed in reset. You now are ready to configure the I2C controller. Once configuration is done, you need to enable the I2C controller by releasing the controller from reset. Prior to starting communication, you need to make sure that all status bits are cleared and no pending interrupts exist. Once the bus is determined to be available (the bus is not busy), the I2C is ready to proceed with the desired communication.

18	Inter-Integrated Circuit (I2C) Peripheral	SPRUEN0D –March 2011
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Texas Instruments TMS320C642X manual Initialization, Software Reset Considerations, Hardware Reset Considerations

Contents

Users Guide Submit Documentation Feedback Revision History Appendix a List of Figures List of Tables Read This First Features Features Not SupportedPurpose of the Peripheral Functional Block Diagram Industry Standards Compliance Statement Bus Structure Multiple I2C Modules Connected Clocking Diagram for the I2C Peripheral Clock Generation Signal Descriptions Clock SynchronizationInput and Output Voltage Levels Start and Stop Conditions Data Validity Serial Data Formats 1 7-Bit Addressing Format Free Data Format Using a Repeated Start Condition2 10-Bit Addressing Format ACK Operating Modes Operating Mode DescriptionEndianness Considerations Operating Modes of the I2C Peripheral Nack Bit Generation Nack Bit GenerationWays to Generate a Nack Bit I2C Peripheral Condition Basic Optional Arbitration Procedure Between Two Master-Transmitters Arbitration Hardware Reset Considerations Reset ConsiderationsSoftware Reset Considerations Initialization Configuring the I2C in Slave Receiver and Transmitter Mode Peripheral Architecture Power Management Interrupt SupportDMA Events Generated by the I2C Peripheral Emulation Considerations Inter-Integrated Circuit I2C RegistersAcronym Register Description Oaddr I2C Own Address Register IcoarI2C Own Address Register Icoar Field Descriptions Bit Field Value Description SCD Icxrdy Icrrdy Ardy Nack I2C Interrupt Mask Register IcimrI2C Interrupt Mask Register Icimr Field Descriptions AAS Sdir Nacksnt Rsfull Xsmt I2C Interrupt Status Register IcstrI2C Interrupt Status Register Icstr Field Descriptions Sdir Bit Field AD0 An acknowledge bit ACK has been sent by the receiver 2 I2C Clock High-Time Divider Register Icclkh I2C Clock Divider Registers Icclkl and Icclkh1 I2C Clock Low-Time Divider Register Icclkl Iccl I2C Data Count Register Iccnt I2C Data Count Register Iccnt Field DescriptionsIcdc I2C Data Receive Register Icdrr Field Descriptions I2C Data Receive Register IcdrrI2C Slave Address Register Icsar I2C Slave Address Register Icsar Field Descriptions I2C Data Transmit Register Icdxr I2C Data Transmit Register Icdxr Field Descriptions I2C Mode Register Icmdr I2C Mode Register Icmdr Field Descriptions RM bit is dont care Icmdr Bit Bus Activity Description How the MST and FDF Bits Affect the Role of TRX Bit I2C State Function of TRX Bit 10 I2C Interrupt Vector Register Icivr I2C Interrupt Vector Register Icivr Field DescriptionsIntcode Ignack BCM R/W-0 R/W-1 11 I2C Extended Mode Register IcemdrI2C Extended Mode Register Icemdr Field Descriptions Ignack 12 I2C Prescaler Register Icpsc I2C Prescaler Register Icpsc Field DescriptionsIpsc Type 13 I2C Peripheral Identification Register ICPID114 I2C Peripheral Identification Register ICPID2 I2C Document Revision History Reference Additions/Modifications/Deletions Rfid Products ApplicationsDSP TI E2E Community Home