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2	SPRUEN0D – March 2011

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Texas Instruments TMS320C642X manual Submit Documentation Feedback

Contents

Users Guide Submit Documentation Feedback Revision History Appendix a List of Figures List of Tables Read This First Purpose of the Peripheral FeaturesFeatures Not Supported Functional Block Diagram Industry Standards Compliance Statement Bus Structure Multiple I2C Modules Connected Clocking Diagram for the I2C Peripheral Clock Generation Input and Output Voltage Levels Signal DescriptionsClock Synchronization Start and Stop Conditions Data Validity Serial Data Formats 1 7-Bit Addressing Format Free Data Format Using a Repeated Start Condition2 10-Bit Addressing Format ACK Operating Modes Operating Mode DescriptionEndianness Considerations Operating Modes of the I2C Peripheral Nack Bit Generation Nack Bit GenerationWays to Generate a Nack Bit I2C Peripheral Condition Basic Optional Arbitration Procedure Between Two Master-Transmitters Arbitration Hardware Reset Considerations Reset ConsiderationsSoftware Reset Considerations Initialization Configuring the I2C in Slave Receiver and Transmitter Mode Peripheral Architecture DMA Events Generated by the I2C Peripheral Power ManagementInterrupt Support Acronym Register Description Emulation ConsiderationsInter-Integrated Circuit I2C Registers Oaddr I2C Own Address Register IcoarI2C Own Address Register Icoar Field Descriptions Bit Field Value Description SCD Icxrdy Icrrdy Ardy Nack I2C Interrupt Mask Register IcimrI2C Interrupt Mask Register Icimr Field Descriptions AAS Sdir Nacksnt Rsfull Xsmt I2C Interrupt Status Register IcstrI2C Interrupt Status Register Icstr Field Descriptions Sdir Bit Field AD0 An acknowledge bit ACK has been sent by the receiver 2 I2C Clock High-Time Divider Register Icclkh I2C Clock Divider Registers Icclkl and Icclkh1 I2C Clock Low-Time Divider Register Icclkl Iccl Icdc I2C Data Count Register IccntI2C Data Count Register Iccnt Field Descriptions I2C Data Receive Register Icdrr Field Descriptions I2C Data Receive Register IcdrrI2C Slave Address Register Icsar I2C Slave Address Register Icsar Field Descriptions I2C Data Transmit Register Icdxr I2C Data Transmit Register Icdxr Field Descriptions I2C Mode Register Icmdr I2C Mode Register Icmdr Field Descriptions RM bit is dont care Icmdr Bit Bus Activity Description How the MST and FDF Bits Affect the Role of TRX Bit I2C State Function of TRX Bit Intcode 10 I2C Interrupt Vector Register IcivrI2C Interrupt Vector Register Icivr Field Descriptions Ignack BCM R/W-0 R/W-1 11 I2C Extended Mode Register IcemdrI2C Extended Mode Register Icemdr Field Descriptions Ignack Ipsc 12 I2C Prescaler Register IcpscI2C Prescaler Register Icpsc Field Descriptions Type 13 I2C Peripheral Identification Register ICPID114 I2C Peripheral Identification Register ICPID2 I2C Document Revision History Reference Additions/Modifications/Deletions Rfid Products ApplicationsDSP TI E2E Community Home