I2C Interrupt Mask Register Icimr | Texas Instruments TMS320C642X

Registers

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3.2I2C Interrupt Mask Register (ICIMR)

The I2C interrupt mask register (ICIMR) is used to individually enable or disable I2C interrupt requests. The I2C interrupt mask register (ICIMR) is shown in Figure 14 and described Table 6.

Figure 14. I2C Interrupt Mask Register (ICIMR)

31								8
			Reserved

				R-0
7	6	5	4	3		2	1	0

Reserved	AAS	SCD	ICXRDY		ICRRDY	ARDY	NACK	AL

R-0	R/W-0	R/W-0	R/W-0		R/W-0	R/W-0	R/W-0	R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

Table 6. I2C Interrupt Mask Register (ICIMR) Field Descriptions

Bit	Field	Value	Description

31-7	Reserved	0	These reserved bit locations are always read as zeros. A value written to this field has no effect.

6	AAS		Address-as-slave interrupt enable bit.
		0	Interrupt request is disabled.
		1	Interrupt request is enabled.

5	SCD		Stop condition detected interrupt enable bit.
		0	Interrupt request is disabled.
		1	Interrupt request is enabled.

4	ICXRDY		Transmit-data-ready interrupt enable bit.
		0	Interrupt request is disabled.
		1	Interrupt request is enabled.

3	ICRRDY		Receive-data-ready interrupt enable bit.
		0	Interrupt request is disabled.
		1	Interrupt request is enabled.

2	ARDY		Register-access-ready interrupt enable bit.
		0	Interrupt request is disabled.
		1	Interrupt request is enabled.

1	NACK		No-acknowledgment interrupt enable bit.
		0	Interrupt request is disabled.
		1	Interrupt request is enabled.

0	AL		Arbitration-lost interrupt enable bit
		0	Interrupt request is disabled.
		1	Interrupt request is enabled.

24	Inter-Integrated Circuit (I2C) Peripheral	SPRUEN0D –March 2011
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Image 24

Texas Instruments TMS320C642X I2C Interrupt Mask Register Icimr Field Descriptions, SCD Icxrdy Icrrdy Ardy Nack, Aas

Contents

Users Guide Submit Documentation Feedback Revision History Appendix a List of Figures List of Tables Read This First Features Features Not SupportedPurpose of the Peripheral Functional Block Diagram Industry Standards Compliance Statement Bus Structure Multiple I2C Modules Connected Clocking Diagram for the I2C Peripheral Clock Generation Signal Descriptions Clock SynchronizationInput and Output Voltage Levels Start and Stop Conditions Data Validity Serial Data Formats 1 7-Bit Addressing Format Using a Repeated Start Condition 2 10-Bit Addressing FormatFree Data Format ACK Operating Mode Description Endianness ConsiderationsOperating Modes Operating Modes of the I2C Peripheral Nack Bit Generation Ways to Generate a Nack BitNack Bit Generation I2C Peripheral Condition Basic Optional Arbitration Procedure Between Two Master-Transmitters Arbitration Reset Considerations Software Reset ConsiderationsHardware Reset Considerations Initialization Configuring the I2C in Slave Receiver and Transmitter Mode Peripheral Architecture Power Management Interrupt SupportDMA Events Generated by the I2C Peripheral Emulation Considerations Inter-Integrated Circuit I2C RegistersAcronym Register Description I2C Own Address Register Icoar I2C Own Address Register Icoar Field DescriptionsOaddr Bit Field Value Description I2C Interrupt Mask Register Icimr I2C Interrupt Mask Register Icimr Field DescriptionsSCD Icxrdy Icrrdy Ardy Nack AAS I2C Interrupt Status Register Icstr I2C Interrupt Status Register Icstr Field DescriptionsSdir Nacksnt Rsfull Xsmt Sdir Bit Field AD0 An acknowledge bit ACK has been sent by the receiver I2C Clock Divider Registers Icclkl and Icclkh 1 I2C Clock Low-Time Divider Register Icclkl2 I2C Clock High-Time Divider Register Icclkh Iccl I2C Data Count Register Iccnt I2C Data Count Register Iccnt Field DescriptionsIcdc I2C Data Receive Register Icdrr I2C Slave Address Register IcsarI2C Data Receive Register Icdrr Field Descriptions I2C Slave Address Register Icsar Field Descriptions I2C Data Transmit Register Icdxr I2C Data Transmit Register Icdxr Field Descriptions I2C Mode Register Icmdr I2C Mode Register Icmdr Field Descriptions RM bit is dont care Icmdr Bit Bus Activity Description How the MST and FDF Bits Affect the Role of TRX Bit I2C State Function of TRX Bit 10 I2C Interrupt Vector Register Icivr I2C Interrupt Vector Register Icivr Field DescriptionsIntcode 11 I2C Extended Mode Register Icemdr I2C Extended Mode Register Icemdr Field DescriptionsIgnack BCM R/W-0 R/W-1 Ignack 12 I2C Prescaler Register Icpsc I2C Prescaler Register Icpsc Field DescriptionsIpsc 13 I2C Peripheral Identification Register ICPID1 14 I2C Peripheral Identification Register ICPID2Type I2C Document Revision History Reference Additions/Modifications/Deletions Products Applications DSPRfid TI E2E Community Home