Type, I2C | Texas Instruments TMS320C642X guide

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Registers

3.13 I2C Peripheral Identification Register (ICPID1)

The I2C peripheral identification registers (ICPID1) contain identification data (class, revision, and type) for the peripheral.

The I2C peripheral identification register (ICPID1) is shown in Figure 27 and described in Table 20.

Figure 27. I2C Peripheral Identification Register 1 (ICPID1)

31				16
	Reserved
		R-0
15	8	7		0

Class				Revision
R-1h				R-6h

LEGEND: R = Read only; -n= value after reset

Table 20. I2C Peripheral Identification Register 1 (ICPID1) Field Descriptions

Bit	Field	Value	Description

31-16	Reserved	0	These reserved bit locations are always read as zeros. A value written to this field has no effect.

15-8	Class		Identifies class of peripheral.
		1h	Serial port

7-0	Revision		Identifies revision of peripheral.
		6h	Current revision of peripheral.

3.14 I2C Peripheral Identification Register (ICPID2)

The I2C peripheral identification register (ICPID2) is shown in Figure 28 and described in Table 21.

Figure 28. I2C Peripheral Identification Register 2 (ICPID2)

31				16
	Reserved
		R-0
15	8	7		0

	Reserved			TYPE
	R-0			R-5h

LEGEND: R = Read only; -n= value after reset

Table 21. I2C Peripheral Identification Register 2 (ICPID2) Field Descriptions

Bit	Field	Value	Description

31-8	Reserved	0	These reserved bit locations are always read as zeros. A value written to this field has no effect.

7-0	TYPE		Identifies type of peripheral.
		5h	I2C

SPRUEN0D –March 2011	Inter-Integrated Circuit (I2C) Peripheral	39
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Texas Instruments TMS320C642X manual 13 I2C Peripheral Identification Register ICPID1, Type

Contents

Users Guide Submit Documentation Feedback Appendix a Revision History List of Figures List of Tables Read This First Features Features Not SupportedPurpose of the Peripheral Industry Standards Compliance Statement Functional Block Diagram Multiple I2C Modules Connected Bus Structure Clock Generation Clocking Diagram for the I2C Peripheral Signal Descriptions Clock SynchronizationInput and Output Voltage Levels Data Validity Start and Stop Conditions 1 7-Bit Addressing Format Serial Data Formats ACK Using a Repeated Start Condition2 10-Bit Addressing Format Free Data Format Operating Modes of the I2C Peripheral Operating Mode DescriptionEndianness Considerations Operating Modes I2C Peripheral Condition Basic Optional Nack Bit GenerationWays to Generate a Nack Bit Nack Bit Generation Arbitration Arbitration Procedure Between Two Master-Transmitters Initialization Reset ConsiderationsSoftware Reset Considerations Hardware Reset Considerations Configuring the I2C in Slave Receiver and Transmitter Mode Peripheral Architecture Power Management Interrupt SupportDMA Events Generated by the I2C Peripheral Emulation Considerations Inter-Integrated Circuit I2C RegistersAcronym Register Description Bit Field Value Description I2C Own Address Register IcoarI2C Own Address Register Icoar Field Descriptions Oaddr AAS I2C Interrupt Mask Register IcimrI2C Interrupt Mask Register Icimr Field Descriptions SCD Icxrdy Icrrdy Ardy Nack Sdir I2C Interrupt Status Register IcstrI2C Interrupt Status Register Icstr Field Descriptions Sdir Nacksnt Rsfull Xsmt AD0 Bit Field An acknowledge bit ACK has been sent by the receiver Iccl I2C Clock Divider Registers Icclkl and Icclkh1 I2C Clock Low-Time Divider Register Icclkl 2 I2C Clock High-Time Divider Register Icclkh I2C Data Count Register Iccnt I2C Data Count Register Iccnt Field DescriptionsIcdc I2C Slave Address Register Icsar Field Descriptions I2C Data Receive Register IcdrrI2C Slave Address Register Icsar I2C Data Receive Register Icdrr Field Descriptions I2C Data Transmit Register Icdxr Field Descriptions I2C Data Transmit Register Icdxr I2C Mode Register Icmdr Field Descriptions I2C Mode Register Icmdr RM bit is dont care Bus Activity Description Icmdr Bit I2C State Function of TRX Bit How the MST and FDF Bits Affect the Role of TRX Bit 10 I2C Interrupt Vector Register Icivr I2C Interrupt Vector Register Icivr Field DescriptionsIntcode Ignack 11 I2C Extended Mode Register IcemdrI2C Extended Mode Register Icemdr Field Descriptions Ignack BCM R/W-0 R/W-1 12 I2C Prescaler Register Icpsc I2C Prescaler Register Icpsc Field DescriptionsIpsc I2C 13 I2C Peripheral Identification Register ICPID114 I2C Peripheral Identification Register ICPID2 Type Reference Additions/Modifications/Deletions Document Revision History TI E2E Community Home Products ApplicationsDSP Rfid