Nack Bit Generation | Texas Instruments TMS320C642X instruction

Peripheral Architecture

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2.9NACK Bit Generation

When the I2C peripheral is a receiver (master or slave), it can acknowledge or ignore bits sent by the transmitter. To ignore any new bits, the I2C peripheral must send a no-acknowledge (NACK) bit during the acknowledge cycle on the bus. Table 2 summarizes the various ways the I2C peripheral sends a NACK bit.

		Table 2. Ways to Generate a NACK Bit

		NACK Bit Generation
	I2C Peripheral
	I2C Peripheral
	Condition	Basic	Optional

	Slave-receiver mode	• Disable data transfers (STT = 0 in ICSTR).	Set the NACKMOD bit of ICMDR before the rising
		• Disable data transfers (STT = 0 in ICSTR).	edge of the last data bit you intend to receive.
		• Allow an overrun condition (RSFULL = 1 in	edge of the last data bit you intend to receive.
		• Allow an overrun condition (RSFULL = 1 in
		ICSTR).
		• Reset the peripheral (IRS = 0 in ICMDR)
		.

	Master-receiver mode	• Generate a STOP condition (STOP = 1 in	Set the NACKMOD bit of ICMDR before the rising
	AND	• Generate a STOP condition (STOP = 1 in	edge of the last data bit you intend to receive.
	AND	ICMDR).	edge of the last data bit you intend to receive.
	Repeat mode	ICMDR).
	Repeat mode	• Reset the peripheral (IRS = 0 in ICMDR).
	(RM = 1 in ICMDR)	• Reset the peripheral (IRS = 0 in ICMDR).
	(RM = 1 in ICMDR)

	Master-receiver mode	• If STP = 1 in ICMDR, allow the internal data	Set the NACKMOD bit of ICMDR before the rising
	AND	• If STP = 1 in ICMDR, allow the internal data	edge of the last data bit you intend to receive.
	AND	counter to count down to 0 and force a STOP	edge of the last data bit you intend to receive.
		counter to count down to 0 and force a STOP

	Nonrepeat mode	condition.
	(RM = 0 in ICMDR)	condition.
	(RM = 0 in ICMDR)	• If STP = 0, make STP = 1 to generate a
		• If STP = 0, make STP = 1 to generate a
		STOP condition.
		• Reset the peripheral (IRS = 0 in ICMDR).

16	Inter-Integrated Circuit (I2C) Peripheral	SPRUEN0D –March 2011
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Texas Instruments TMS320C642X Nack Bit Generation, Ways to Generate a Nack Bit, I2C Peripheral Condition Basic Optional

Contents

Users Guide Submit Documentation Feedback Revision History Appendix a List of Figures List of Tables Read This First Features Not Supported FeaturesPurpose of the Peripheral Functional Block Diagram Industry Standards Compliance Statement Bus Structure Multiple I2C Modules Connected Clocking Diagram for the I2C Peripheral Clock Generation Clock Synchronization Signal DescriptionsInput and Output Voltage Levels Start and Stop Conditions Data Validity Serial Data Formats 1 7-Bit Addressing Format Using a Repeated Start Condition 2 10-Bit Addressing FormatFree Data Format ACK Operating Mode Description Endianness ConsiderationsOperating Modes Operating Modes of the I2C Peripheral Nack Bit Generation Ways to Generate a Nack BitNack Bit Generation I2C Peripheral Condition Basic Optional Arbitration Procedure Between Two Master-Transmitters Arbitration Reset Considerations Software Reset ConsiderationsHardware Reset Considerations Initialization Configuring the I2C in Slave Receiver and Transmitter Mode Peripheral Architecture Interrupt Support Power ManagementDMA Events Generated by the I2C Peripheral Inter-Integrated Circuit I2C Registers Emulation ConsiderationsAcronym Register Description I2C Own Address Register Icoar I2C Own Address Register Icoar Field DescriptionsOaddr Bit Field Value Description I2C Interrupt Mask Register Icimr I2C Interrupt Mask Register Icimr Field DescriptionsSCD Icxrdy Icrrdy Ardy Nack AAS I2C Interrupt Status Register Icstr I2C Interrupt Status Register Icstr Field DescriptionsSdir Nacksnt Rsfull Xsmt Sdir Bit Field AD0 An acknowledge bit ACK has been sent by the receiver I2C Clock Divider Registers Icclkl and Icclkh 1 I2C Clock Low-Time Divider Register Icclkl2 I2C Clock High-Time Divider Register Icclkh Iccl I2C Data Count Register Iccnt Field Descriptions I2C Data Count Register IccntIcdc I2C Data Receive Register Icdrr I2C Slave Address Register IcsarI2C Data Receive Register Icdrr Field Descriptions I2C Slave Address Register Icsar Field Descriptions I2C Data Transmit Register Icdxr I2C Data Transmit Register Icdxr Field Descriptions I2C Mode Register Icmdr I2C Mode Register Icmdr Field Descriptions RM bit is dont care Icmdr Bit Bus Activity Description How the MST and FDF Bits Affect the Role of TRX Bit I2C State Function of TRX Bit I2C Interrupt Vector Register Icivr Field Descriptions 10 I2C Interrupt Vector Register IcivrIntcode 11 I2C Extended Mode Register Icemdr I2C Extended Mode Register Icemdr Field DescriptionsIgnack BCM R/W-0 R/W-1 Ignack I2C Prescaler Register Icpsc Field Descriptions 12 I2C Prescaler Register IcpscIpsc 13 I2C Peripheral Identification Register ICPID1 14 I2C Peripheral Identification Register ICPID2Type I2C Document Revision History Reference Additions/Modifications/Deletions Products Applications DSPRfid TI E2E Community Home