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Texas Instruments TMS320C642x DSP manual Signal Descriptions, DDR2 Memory Controller Signals

Models: TMS320C642x DSP

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2.3Signal Descriptions

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Peripheral Architecture

2.3Signal Descriptions

The DDR2 memory controller signals are shown in Figure 3 and described in Table 2. The following features are included:

∙The maximum data bus is 32-bits wide.

∙The address bus is 13-bits wide with an additional 3 bank address pins.

∙Two differential output clocks driven by internal clock sources.

∙Command signals: Row and column address strobe, write enable strobe, data strobe, and data mask.

∙One chip select signal and one clock enable signal.

Figure 3. DDR2 Memory Controller Signals

		DDR_CLK
		DDR_CLK
		DDR_CKE
		DDR_CS
		DDR_WE
		DDR_RAS
	DDR2	DDR_CAS
	memory	DDR_DQM[3:0]
	controller	DDR_DQM[3:0]
	controller	DDR_DQS[3:0]
		DDR_DQS[3:0]
		DDR_BA[2:0]
		DDR_A[12:0]
		DDR_D[31:0]
		200 Ω
		DDR_ZN
		200 Ω
		DDR_ZP

		Table 2. DDR2 Memory Controller Signal Descriptions
Pin	Type	Description
DDR_CLK,	O/Z	Clock: Differential clock outputs.
DDR_CLK
DDR_CKE	O/Z	Clock enable: Active high.
DDR_CS	O/Z	Chip select: Active low.
DDR_WE	O/Z	Write enable strobe: Active low, command output.
DDR_RAS	O/Z	Row address strobe: Active low, command output.
DDR_CAS	O/Z	Column address strobe: Active low, command output.
DDR_DQM[3:0]	O/Z	Data mask: Output mask signal for write data.
DDR_DQS[3:0]	I/O/Z	Data strobe: Active high, bi-directional signals. Output with write data, input with read data.
DDR_BA[2:0]	O/Z	Bank address: Output, defining which bank a given command is applied.
DDR_A[12:0]	O/Z	Address: Address bus.
DDR_D[31:0]	I/O/Z	Data: Bi-directional data bus. Input for read data, output for write data.
DDR_ZN,	O	Output impedance control: Required to set the DDR2 output impedance. Connected by way of
DDR_ZP		a 200-ohm resistor to power and ground (see Figure 3). The resistor should be chosen to be
		4 times the desired impedance of the output buffer. By changing the size of the resistor, the
		DDR2 outputs can be tuned to match the board load, if necessary.
SPRUEM4A–November 2007		DDR2 Memory Controller	11
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Texas Instruments TMS320C642x DSP manual Signal Descriptions, DDR2 Memory Controller Signals, Peripheral Architecture

Contents

TMS320C642x DSP DDR2 Memory Controller Users GuideSubmit Documentation Feedback SPRUEM4A-NovemberContents List of Figures List of FiguresList of Tables Notational Conventions Read This FirstPreface About This Manual1 Introduction DDR2 Memory ControllerUsers Guide 1.2 FeaturesFigure 1. Data Paths to DDR2 Memory Controller 1.3 Functional Block Diagram1.4 Supported Use Case Statement 1.5 Industry Standards Compliance Statement2.1.1 Clock Source Figure 2. DDR2 Memory Controller Clock Block Diagram2 Peripheral Architecture 2.1 Clock Control2.1.3 DDR2 Memory Controller Internal Clock Domains 2.1.2 Clock ConfigurationTable 1. PLLC2 Configuration 2.2 Memory MapPeripheral Architecture 2.3 Signal DescriptionsFigure 3. DDR2 Memory Controller Signals Table 2. DDR2 Memory Controller Signal DescriptionsPeripheral Architecture Table 3. DDR2 SDRAM CommandsTable 4. Truth Table for DDR2 SDRAM Commands 2.4 Protocol DescriptionsDDRCKE DDRCS DDRRAS DDRCAS DDRWE DDRA120 DDRBA20 DDRDQM30 Figure 4. Refresh Command2.4.1 Refresh Mode DDRCLK DDRCLKDDRBA20 DDRDQM30 Figure 5. DCAB Command2.4.2 Deactivation DCAB and DEAC DCAB DDRCLK DDRCLK DDRCKE DDRCS DDRRAS DDRCAS DDRWE DDRA12,11 DDRA10Submit Documentation Feedback Figure 6. DEAC CommandPeripheral Architecture DDR2 Memory ControllerDDRA120 Figure 7. ACTV Command2.4.3 Activation ACTV DDRBA20 BANK DDRA10 DDRDQM30 CAS Latency 2.4.4 READ CommandFigure 8. DDR2 READ Command DDRCLK DDRCLK DDRCKE DDRCS DDRRAS DDRCAS DDRWE DDRA120 COLFigure 9. DDR2 WRT Command 2.4.5 Write WRT Command2.4.6 Mode Register Set MRS and EMRS Figure 10. DDR2 MRS and EMRS CommandFigure 11. Byte Alignment Little-Endian Mode 2.5 Memory Width and Byte AlignmentTable 5. Addressable Memory Ranges Table 7. 32-Bit External Memory 2.6 Endianness SupportTable 6. 16-Bit External Memory 2.7 Address Mapping Table 8. Bank Configuration Register Fields for Address MappingDDR2 Memory Controller Table 9. Logical Address-to-DDR2 SDRAM Address Map for 32-Bit SDRAMTable 10. Logical Address-to-DDR2 SDRAM Address Map for 16-bit SDRAM Peripheral ArchitecturePeripheral Architecture Figure 12. Logical Address-to-DDR2 SDRAM Address MapSubmit Documentation Feedback Figure 13. DDR2 SDRAM Column, Row, and Bank AccessPeripheral Architecture DDR2 Memory ControllerTable 11. DDR2 Memory Controller FIFO Description Figure 14. DDR2 Memory Controller FIFO Block Diagram2.8 DDR2 Memory Controller Interface 2.8.1 Command Ordering and Scheduling, Advanced Concept 2.8.3 Possible Race Condition 2.8.2 Command StarvationTable 12. Refresh Urgency Levels 2.9 Refresh Scheduling2.10 Self-Refresh Mode Figure 15. DDR2 Memory Controller Reset Block Diagram 2.11 Reset ConsiderationsTable 13. Reset Sources 2.13 Auto-Initialization Sequence 2.12 VTP IO Buffer CalibrationWrite recovery from autoprecharge. Value of Table 14. DDR2 SDRAM Configuration by MRS CommandTable 15. DDR2 SDRAM Configuration by EMRS1 Command 2.13.1 Initializing Configuration Registers2.13.2 Initializing Following Device Power Up and Device RESET 2.15 DMA Event Support 2.16 Power ManagementFigure 16. DDR2 Memory Controller Power Sleep Controller Diagram 2.14 Interrupt Support2.17 Emulation Considerations 2.16.1 DDR2 Memory Controller Clock Stop Procedure3 Supported Use Cases 3.1 Connecting the DDR2 Memory Controller to DDR2 Memory200 Ω 200 Ω Figure 17. Connecting DDR2 Memory Controller for 32-Bit ConnectionFigure 18. Connecting DDR2 Memory Controller for 16-Bit Connection Supported Use CasesTable 17. DDR2 Memory Refresh Specification 3.2.1 Configuring SDRAM Bank Configuration Register SDBCRTable 16. SDRAM Bank Configuration Register SDBCR Configuration 3.2.2 Configuring SDRAM Refresh Control Register SDRCRTable 20. SDRAM Timing Register 2 SDTIMR2 Configuration 3.2.3 Configuring SDRAM Timing Registers SDTIMR and SDTIMR2Table 19. SDRAM Timing Register SDTIMR Configuration Table 21. DDR PHY Control Register DDRPHYCR Configuration 3.2.4 Configuring DDR PHY Control Register DDRPHYCRDDR2 Memory Controller Registers 4 DDR2 Memory Controller RegistersDDR2 Memory Controller Registers 4.1 SDRAM Status Register SDRSTATFigure 19. SDRAM Status Register SDRSTAT Table 25. SDRAM Status Register SDRSTAT Field DescriptionsDDR2 Memory Controller Registers 4.2 SDRAM Bank Configuration Register SDBCRFigure 20. SDRAM Bank Configuration Register SDBCR Table 26. SDRAM Bank Configuration Register SDBCR Field DescriptionsDDR2 Memory Controller DDR2 Memory Controller RegistersDDR2 Memory Controller Registers 4.3 SDRAM Refresh Control Register SDRCRFigure 21. SDRAM Refresh Control Register SDRCR Table 27. SDRAM Refresh Control Register SDRCR Field DescriptionsDDR2 Memory Controller Registers 4.4 SDRAM Timing Register SDTIMRFigure 22. SDRAM Timing Register SDTIMR Table 28. SDRAM Timing Register SDTIMR Field DescriptionsDDR2 Memory Controller Registers 4.5 SDRAM Timing Register 2 SDTIMR2Figure 23. SDRAM Timing Register 2 SDTIMR2 Table 29. SDRAM Timing Register 2 SDTIMR2 Field DescriptionsFigure 24. Peripheral Bus Burst Priority Register PBBPR 4.6 Peripheral Bus Burst Priority Register PBBPRDDR2 Memory Controller Registers 4.7 Interrupt Raw Register IRRFigure 25. Interrupt Raw Register IRR Table 31. Interrupt Raw Register IRR Field DescriptionsTable 32. Interrupt Masked Register IMR Field Descriptions 4.8 Interrupt Masked Register IMRFigure 26. Interrupt Masked Register IMR DDR2 Memory Controller Registers 4.9 Interrupt Mask Set Register IMSRFigure 27. Interrupt Mask Set Register IMSR Table 33. Interrupt Mask Set Register IMSR Field DescriptionsDDR2 Memory Controller Registers 4.10 Interrupt Mask Clear Register IMCRFigure 28. Interrupt Mask Clear Register IMCR Table 34. Interrupt Mask Clear Register IMCR Field DescriptionsDDR2 Memory Controller Registers 4.11 DDR PHY Control Register DDRPHYCRFigure 29. DDR PHY Control Register DDRPHYCR Table 35. DDR PHY Control Register DDRPHYCR Field DescriptionsDDR2 Memory Controller Registers 4.12 VTP IO Control Register VTPIOCRFigure 30. VTP IO Control Register VTPIOCR Table 36. VTP IO Control Register VTPIOCR Field Descriptions4.13 DDR VTP Register DDRVTPR 4.14 DDR VTP Enable Register DDRVTPERFigure 32. DDR VTP Enable Register DDRVTPER Table 38. DDR VTP Enable Register DDRVTPER Field DescriptionsSection Appendix A Revision HistoryTable A-1. Document Revision History Appendix AApplications power.ti.comIMPORTANT NOTICE Products