Interrupt Raw Register IRR | Texas Instruments TMS320C642x DSP

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DDR2 Memory Controller Registers

4.7Interrupt Raw Register (IRR)

The interrupt raw register (IRR) displays the raw status of the interrupt. If the interrupt condition occurs, the corresponding bit in IRR is set independent of whether or not the interrupt is enabled. The IRR is shown in Figure 25 and described in Table 31.

Figure 25. Interrupt Raw Register (IRR)

31				16
	Reserved
	R-0
15	3	2	1	0
Reserved		LT	Reserved
R-0		R/W1C-0		R-0
LEGEND: R/W = Read/Write; R = Read only; W1C = Write 1 to clear (writing 0 has no effect); -n= value after reset

			Table 31. Interrupt Raw Register (IRR) Field Descriptions
Bit	Field	Value	Description
31-3	Reserved	0	Reserved
2	LT		Line trap. Write a 1 to clear LT and the LTM bit in the interrupt masked register (IMR); a write of 0 has
			no effect.
		0	A line trap condition has not occurred.
		1	Illegal memory access type. See Section 2.14 for more details.
1-0	Reserved	0	Reserved

SPRUEM4A–November 2007	DDR2 Memory Controller	49
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Texas Instruments TMS320C642x DSP manual Interrupt Raw Register IRR Field Descriptions

Contents

Users Guide Submit Documentation Feedback Contents List of Figures List of Tables Read This First Purpose of the Peripheral Features Supported Use Case Statement Functional Block DiagramIndustry Standards Compliance Statement Clock Source Clock Control PLLC2 Configuration Clock ConfigurationMemory Map 3 DDR2 Memory Controller Internal Clock Domains DDR2 Memory Controller Signal Descriptions Signal DescriptionsClock enable Active high Pin Type Description Truth Table for DDR2 Sdram Commands DDR2 Sdram CommandsCommand Function Protocol Descriptions Refresh Command Refresh Mode Deactivation Dcab and Deac Dcab Command Deac Command Activation Actv Actv Command DDR2 Read Command Read Command DDR2 WRT Command Write WRT Command DDR2 MRS and Emrs Command Mode Register Set MRS and Emrs Addressable Memory Ranges Memory Width and Byte Alignment Bit External Memory Endianness Support Address Mapping Bank Configuration Register Fields for Address MappingBit Field Bit Value Bit Description Logical Address-to-DDR2 Sdram Address Map for 16-bit Sdram Logical Address-to-DDR2 Sdram Address Map for 32-Bit Sdram Logical Address-to-DDR2 Sdram Address Map DDR2 Sdram Column, Row, and Bank Access DDR2 Memory Controller Fifo Description DDR2 Memory Controller Interface Command Ordering and Scheduling, Advanced Concept Possible Race Condition Command Starvation Refresh Scheduling Self-Refresh ModeRefresh Urgency Levels Urgency Level Description Reset Sources Reset ConsiderationsReset Signal Reset Source Auto-Initialization Sequence VTP IO Buffer Calibration DDR2 Sdram Configuration by EMRS1 Command DDR2 Sdram Configuration by MRS CommandInitializing Configuration Registers DDR2 Memory Controller Peripheral Architecture Interrupt Support Power ManagementDMA Event Support Emulation Considerations Supported Use Cases Connecting the DDR2 Memory Controller to DDR2 Memory Connecting DDR2 Memory Controller for 32-Bit Connection Sdram Bank Configuration Register Sdbcr Configuration Configuring Sdram Bank Configuration Register SdbcrConfiguring Sdram Refresh Control Register Sdrcr DDR2 Memory Refresh Specification Sdram Timing Register Sdtimr Configuration Configuring Sdram Timing Registers Sdtimr and SDTIMR2Sdram Timing Register 2 SDTIMR2 Configuration DDR2 Data Register Field Manual Data Manual Formula DDR PHY Control Register Ddrphycr Configuration Configuring DDR PHY Control Register DdrphycrRegister Field Name Description D31-0 Mode D63-32Acronym Register Description DDR VTP Register Sdram Status Register Sdrstat Field Descriptions Sdram Status Register SdrstatBit Field Sdram Bank Configuration Register Sdbcr Field Descriptions Sdram Bank Configuration Register SdbcrBit Field Value Description Reserved Reserved. Always write a 0 to this bit Sdram Refresh Control Register Sdrcr Field Descriptions Sdram Refresh Control Register Sdrcr Sdram Timing Register Sdtimr Field Descriptions Sdram Timing Register Sdtimr Sdram Timing Register 2 SDTIMR2 Field Descriptions Sdram Timing Register 2 SDTIMR2 Peripheral Bus Burst Priority Register Pbbpr Peripheral Bus Burst Priority Register Pbbpr Interrupt Raw Register IRR Field Descriptions Interrupt Raw Register IRR Interrupt Masked Register IMR Field Descriptions Interrupt Masked Register IMR Interrupt Mask Set Register Imsr Field Descriptions Interrupt Mask Set Register Imsr Interrupt Mask Clear Register Imcr Field Descriptions Interrupt Mask Clear Register Imcr DDR PHY Control Register Ddrphycr Field Descriptions DDR PHY Control Register Ddrphycr VTP IO Control Register Vtpiocr Field Descriptions VTP IO Control Register Vtpiocr DDR VTP Enable Register Ddrvtper Field Descriptions DDR VTP Enable Register DdrvtperDDR VTP Register Ddrvtpr DDR VTP Register Ddrvtpr Field Descriptions Additions/Modifications/Deletions Table A-1. Document Revision History Important Notice