Texas Instruments TMS320C642x DSP manual Supported Use Cases

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Supported Use Cases

3Supported Use Cases

The DDR2 memory controller allows a high degree of programmability for shaping DDR2 accesses. The programmability inherent to the DDR2 memory controller provides the DDR2 memory controller with the flexibility to interface with a variety of DDR2 devices. By programming the SDRAM bank configuration register (SDBCR), SDRAM refresh control register (SDRCR), SDRAM timing register (SDTIMR), and SDRAM timing register 2 (SDTIMR2), the DDR2 memory controller can be configured to meet the data sheet specification for JESD79D-2A compliant DDR2 SDRAM.

This section presents an example describing how to interface the DDR2 memory controller to a JESD79D DDR2-400 1-Gb device. The DDR2 memory controller is assumed to be operating at 133 MHZ.

3.1Connecting the DDR2 Memory Controller to DDR2 Memory

The following figures show how to connect the DDR2 memory controller to a DDR2 device. Figure 17 displays a 32-bit interface; therefore, two 16-bit DDR2 devices are connected to the DDR2 memory controller. From Figure 17, you can see that the data bus, data strobe, and data mask (byte enable) signals are point-to-point where as all other address, control, and clocks are not. Figure 18 displays a

16-bit interface; therefore, all signals are point-to-point. See the device-specific data manual for the data bus widths that are supported.

3.2Configuring Memory-Mapped Registers to Meet DDR2-400 Specification

As previously stated, four memory-mapped registers must be programmed to configure the DDR2 memory controller to meet the data sheet specification of the attached DDR2 device. The registers are:

∙SDRAM bank configuration register (SDBCR)

∙SDRAM refresh control register (SDRCR)

∙SDRAM timing register (SDTIMR)

∙SDRAM timing register 2 (SDTIMR2)

In addition to these registers, the DDR PHY control register (DDRPHYCR) must also be programmed. The configuration of DDRPHYCR is not dependent on the DDR2 device specification but rather on the board layout.

The following sections describe how to configure each of these registers. See Section 4 for more information on the DDR2 memory controller registers.

36 DDR2 Memory Controller SPRUEM4A–November 2007

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