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TMS320C642x DSP manual SPRUEM4A-November, Submit Documentation Feedback
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TMS320C642x DSP
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Functional Block Diagram
Clock Configuration
Reset Considerations
DDR2 SDRAM Commands
Signal Descriptions
Power Management
Features
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SPRUEM4A–November
2007
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Contents
Users Guide
TMS320C642x DSP DDR2 Memory Controller
SPRUEM4A-November
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Contents
List of Figures
List of Figures
List of Tables
About This Manual
Read This First
Preface
Notational Conventions
1.2 Features
DDR2 Memory Controller
Users Guide
1 Introduction
1.5 Industry Standards Compliance Statement
1.3 Functional Block Diagram
1.4 Supported Use Case Statement
Figure 1. Data Paths to DDR2 Memory Controller
2.1 Clock Control
Figure 2. DDR2 Memory Controller Clock Block Diagram
2 Peripheral Architecture
2.1.1 Clock Source
2.2 Memory Map
2.1.2 Clock Configuration
Table 1. PLLC2 Configuration
2.1.3 DDR2 Memory Controller Internal Clock Domains
Table 2. DDR2 Memory Controller Signal Descriptions
2.3 Signal Descriptions
Figure 3. DDR2 Memory Controller Signals
Peripheral Architecture
2.4 Protocol Descriptions
Table 3. DDR2 SDRAM Commands
Table 4. Truth Table for DDR2 SDRAM Commands
Peripheral Architecture
DDRCLK DDRCLK
Figure 4. Refresh Command
2.4.1 Refresh Mode
DDRCKE DDRCS DDRRAS DDRCAS DDRWE DDRA120 DDRBA20 DDRDQM30
DCAB DDRCLK DDRCLK DDRCKE DDRCS DDRRAS DDRCAS DDRWE DDRA12,11 DDRA10
Figure 5. DCAB Command
2.4.2 Deactivation DCAB and DEAC
DDRBA20 DDRDQM30
DDR2 Memory Controller
Figure 6. DEAC Command
Peripheral Architecture
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DDRA120
Figure 7. ACTV Command
2.4.3 Activation ACTV
DDRCLK DDRCLK DDRCKE DDRCS DDRRAS DDRCAS DDRWE DDRA120 COL
2.4.4 READ Command
Figure 8. DDR2 READ Command
DDRBA20 BANK DDRA10 DDRDQM30 CAS Latency
2.4.5 Write WRT Command
Figure 9. DDR2 WRT Command
Figure 10. DDR2 MRS and EMRS Command
2.4.6 Mode Register Set MRS and EMRS
Figure 11. Byte Alignment Little-Endian Mode
2.5 Memory Width and Byte Alignment
Table 5. Addressable Memory Ranges
Table 7. 32-Bit External Memory
2.6 Endianness Support
Table 6. 16-Bit External Memory
Table 8. Bank Configuration Register Fields for Address Mapping
2.7 Address Mapping
Peripheral Architecture
Table 9. Logical Address-to-DDR2 SDRAM Address Map for 32-Bit SDRAM
Table 10. Logical Address-to-DDR2 SDRAM Address Map for 16-bit SDRAM
DDR2 Memory Controller
Figure 12. Logical Address-to-DDR2 SDRAM Address Map
Peripheral Architecture
DDR2 Memory Controller
Figure 13. DDR2 SDRAM Column, Row, and Bank Access
Peripheral Architecture
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Table 11. DDR2 Memory Controller FIFO Description
Figure 14. DDR2 Memory Controller FIFO Block Diagram
2.8 DDR2 Memory Controller Interface
2.8.1 Command Ordering and Scheduling, Advanced Concept
2.8.2 Command Starvation
2.8.3 Possible Race Condition
Table 12. Refresh Urgency Levels
2.9 Refresh Scheduling
2.10 Self-Refresh Mode
Figure 15. DDR2 Memory Controller Reset Block Diagram
2.11 Reset Considerations
Table 13. Reset Sources
2.12 VTP IO Buffer Calibration
2.13 Auto-Initialization Sequence
2.13.1 Initializing Configuration Registers
Table 14. DDR2 SDRAM Configuration by MRS Command
Table 15. DDR2 SDRAM Configuration by EMRS1 Command
Write recovery from autoprecharge. Value of
2.13.2 Initializing Following Device Power Up and Device RESET
2.14 Interrupt Support
2.16 Power Management
Figure 16. DDR2 Memory Controller Power Sleep Controller Diagram
2.15 DMA Event Support
2.16.1 DDR2 Memory Controller Clock Stop Procedure
2.17 Emulation Considerations
3.1 Connecting the DDR2 Memory Controller to DDR2 Memory
3 Supported Use Cases
Supported Use Cases
Figure 17. Connecting DDR2 Memory Controller for 32-Bit Connection
Figure 18. Connecting DDR2 Memory Controller for 16-Bit Connection
200 Ω 200 Ω
3.2.2 Configuring SDRAM Refresh Control Register SDRCR
3.2.1 Configuring SDRAM Bank Configuration Register SDBCR
Table 16. SDRAM Bank Configuration Register SDBCR Configuration
Table 17. DDR2 Memory Refresh Specification
Table 20. SDRAM Timing Register 2 SDTIMR2 Configuration
3.2.3 Configuring SDRAM Timing Registers SDTIMR and SDTIMR2
Table 19. SDRAM Timing Register SDTIMR Configuration
3.2.4 Configuring DDR PHY Control Register DDRPHYCR
Table 21. DDR PHY Control Register DDRPHYCR Configuration
4 DDR2 Memory Controller Registers
DDR2 Memory Controller Registers
Table 25. SDRAM Status Register SDRSTAT Field Descriptions
4.1 SDRAM Status Register SDRSTAT
Figure 19. SDRAM Status Register SDRSTAT
DDR2 Memory Controller Registers
Table 26. SDRAM Bank Configuration Register SDBCR Field Descriptions
4.2 SDRAM Bank Configuration Register SDBCR
Figure 20. SDRAM Bank Configuration Register SDBCR
DDR2 Memory Controller Registers
DDR2 Memory Controller Registers
DDR2 Memory Controller
Table 27. SDRAM Refresh Control Register SDRCR Field Descriptions
4.3 SDRAM Refresh Control Register SDRCR
Figure 21. SDRAM Refresh Control Register SDRCR
DDR2 Memory Controller Registers
Table 28. SDRAM Timing Register SDTIMR Field Descriptions
4.4 SDRAM Timing Register SDTIMR
Figure 22. SDRAM Timing Register SDTIMR
DDR2 Memory Controller Registers
Table 29. SDRAM Timing Register 2 SDTIMR2 Field Descriptions
4.5 SDRAM Timing Register 2 SDTIMR2
Figure 23. SDRAM Timing Register 2 SDTIMR2
DDR2 Memory Controller Registers
4.6 Peripheral Bus Burst Priority Register PBBPR
Figure 24. Peripheral Bus Burst Priority Register PBBPR
Table 31. Interrupt Raw Register IRR Field Descriptions
4.7 Interrupt Raw Register IRR
Figure 25. Interrupt Raw Register IRR
DDR2 Memory Controller Registers
Table 32. Interrupt Masked Register IMR Field Descriptions
4.8 Interrupt Masked Register IMR
Figure 26. Interrupt Masked Register IMR
Table 33. Interrupt Mask Set Register IMSR Field Descriptions
4.9 Interrupt Mask Set Register IMSR
Figure 27. Interrupt Mask Set Register IMSR
DDR2 Memory Controller Registers
Table 34. Interrupt Mask Clear Register IMCR Field Descriptions
4.10 Interrupt Mask Clear Register IMCR
Figure 28. Interrupt Mask Clear Register IMCR
DDR2 Memory Controller Registers
Table 35. DDR PHY Control Register DDRPHYCR Field Descriptions
4.11 DDR PHY Control Register DDRPHYCR
Figure 29. DDR PHY Control Register DDRPHYCR
DDR2 Memory Controller Registers
Table 36. VTP IO Control Register VTPIOCR Field Descriptions
4.12 VTP IO Control Register VTPIOCR
Figure 30. VTP IO Control Register VTPIOCR
DDR2 Memory Controller Registers
Table 38. DDR VTP Enable Register DDRVTPER Field Descriptions
4.14 DDR VTP Enable Register DDRVTPER
Figure 32. DDR VTP Enable Register DDRVTPER
4.13 DDR VTP Register DDRVTPR
Appendix A
Appendix A Revision History
Table A-1. Document Revision History
Section
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