Texas Instruments TMS320C642x DSP manual

www.ti.com

DDR2 Memory Controller Registers

4.3SDRAM Refresh Control Register (SDRCR)

The SDRAM refresh control register (SDRCR) is used to configure the DDR2 memory controller to:

∙Enter and Exit the self-refresh state.

∙Enable and disable MCLK, stopping when in the self-refresh state.

∙Meet the refresh requirement of the attached DDR2 device by programming the rate at which the DDR2 memory controller issues autorefresh commands.

The SDRCR is shown in Figure 21 and described in Table 27.

Figure 21. SDRAM Refresh Control Register (SDRCR)

31	30	29	24	23	22	16
SR	MCLKSTOPEN		Reserved	Rsvd		Reserved
R/W-0	R/W-0		R-0	R/W-0		R-0
15						0
			RR
			R/W-884h
LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

Table 27. SDRAM Refresh Control Register (SDRCR) Field Descriptions

Bit	Field	Value	Description
31	SR		Self refresh.
		0	DDR2 memory controller exits the self-refresh mode.
		1	DDR2 memory controller enters the self-refresh mode.
30	MCLKSTOPEN		MCLK stop enable.
		0	Disables MCLK stopping, MCLK may not be stopped.
		1	Enables MCLK stopping, MCLK may be stopped. The SR bit must be set to 1 before setting the
			MCLKSTOPEN bit to 1.
29-24	Reserved	0	Reserved
23	Reserved	0	Reserved. Always write 0 to this bit.
22-16	Reserved	0	Reserved
15-0	RR	0-FFFFh	Refresh rate. Defines the rate at which the attached DDR2 devices will be refreshed. The value

of this field may be calculated with the following equation:

RR = DDR2 clock frequency (in MHZ) × DDR2 refresh rate (in μs)

where DDR2 refresh rate is derived from the DDR2 data sheet. Writing a value < 0100h to this field causes it to be loaded with the value 2 × T_RFC from the SDRAM timing register (SDTIMR).

SPRUEM4A–November 2007	DDR2 Memory Controller	45
Submit Documentation Feedback

Image 45

Texas Instruments TMS320C642x DSP manual Sdram Refresh Control Register Sdrcr

Contents

Users Guide Submit Documentation Feedback Contents List of Figures List of Tables Read This First Purpose of the Peripheral Features Functional Block Diagram Supported Use Case StatementIndustry Standards Compliance Statement Clock Source Clock Control PLLC2 Configuration Clock ConfigurationMemory Map 3 DDR2 Memory Controller Internal Clock Domains DDR2 Memory Controller Signal Descriptions Signal DescriptionsClock enable Active high Pin Type Description Truth Table for DDR2 Sdram Commands DDR2 Sdram CommandsCommand Function Protocol Descriptions Refresh Command Refresh Mode Deactivation Dcab and Deac Dcab Command Deac Command Activation Actv Actv Command DDR2 Read Command Read Command DDR2 WRT Command Write WRT Command DDR2 MRS and Emrs Command Mode Register Set MRS and Emrs Addressable Memory Ranges Memory Width and Byte Alignment Bit External Memory Endianness Support Bank Configuration Register Fields for Address Mapping Address MappingBit Field Bit Value Bit Description Logical Address-to-DDR2 Sdram Address Map for 16-bit Sdram Logical Address-to-DDR2 Sdram Address Map for 32-Bit Sdram Logical Address-to-DDR2 Sdram Address Map DDR2 Sdram Column, Row, and Bank Access DDR2 Memory Controller Fifo Description DDR2 Memory Controller Interface Command Ordering and Scheduling, Advanced Concept Possible Race Condition Command Starvation Refresh Scheduling Self-Refresh ModeRefresh Urgency Levels Urgency Level Description Reset Considerations Reset SourcesReset Signal Reset Source Auto-Initialization Sequence VTP IO Buffer Calibration DDR2 Sdram Configuration by EMRS1 Command DDR2 Sdram Configuration by MRS CommandInitializing Configuration Registers DDR2 Memory Controller Peripheral Architecture Power Management Interrupt SupportDMA Event Support Emulation Considerations Supported Use Cases Connecting the DDR2 Memory Controller to DDR2 Memory Connecting DDR2 Memory Controller for 32-Bit Connection Sdram Bank Configuration Register Sdbcr Configuration Configuring Sdram Bank Configuration Register SdbcrConfiguring Sdram Refresh Control Register Sdrcr DDR2 Memory Refresh Specification Sdram Timing Register Sdtimr Configuration Configuring Sdram Timing Registers Sdtimr and SDTIMR2Sdram Timing Register 2 SDTIMR2 Configuration DDR2 Data Register Field Manual Data Manual Formula Configuring DDR PHY Control Register Ddrphycr DDR PHY Control Register Ddrphycr ConfigurationRegister Field Name Description D31-0 Mode D63-32Acronym Register Description DDR VTP Register Sdram Status Register Sdrstat Sdram Status Register Sdrstat Field DescriptionsBit Field Sdram Bank Configuration Register Sdbcr Sdram Bank Configuration Register Sdbcr Field DescriptionsBit Field Value Description Reserved Reserved. Always write a 0 to this bit Sdram Refresh Control Register Sdrcr Field Descriptions Sdram Refresh Control Register Sdrcr Sdram Timing Register Sdtimr Field Descriptions Sdram Timing Register Sdtimr Sdram Timing Register 2 SDTIMR2 Field Descriptions Sdram Timing Register 2 SDTIMR2 Peripheral Bus Burst Priority Register Pbbpr Peripheral Bus Burst Priority Register Pbbpr Interrupt Raw Register IRR Field Descriptions Interrupt Raw Register IRR Interrupt Masked Register IMR Field Descriptions Interrupt Masked Register IMR Interrupt Mask Set Register Imsr Field Descriptions Interrupt Mask Set Register Imsr Interrupt Mask Clear Register Imcr Field Descriptions Interrupt Mask Clear Register Imcr DDR PHY Control Register Ddrphycr Field Descriptions DDR PHY Control Register Ddrphycr VTP IO Control Register Vtpiocr Field Descriptions VTP IO Control Register Vtpiocr DDR VTP Enable Register Ddrvtper Field Descriptions DDR VTP Enable Register DdrvtperDDR VTP Register Ddrvtpr DDR VTP Register Ddrvtpr Field Descriptions Additions/Modifications/Deletions Table A-1. Document Revision History Important Notice