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Texas Instruments TMS320C642x DSP manual Activation ACTV, ACTV Command, DDRA120

Models: TMS320C642x DSP

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Peripheral Architecture

2.4.3Activation (ACTV)

The DDR2 memory controller automatically issues the activate (ACTV) command before a read or write to a closed row of memory. The ACTV command opens a row of memory, allowing future accesses (reads or writes) with minimum latency. The value of DDR_BA[2:0] selects the bank and the value of A[12:0] selects the row. When the DDR2 memory controller issues an ACTV command, a delay of tRCD is incurred before a read or write command is issued. Figure 7 shows an example of an ACTV command. Reads or writes to the currently active row and bank of memory can achieve much higher throughput than reads or writes to random areas because every time a new row is accessed, the ACTV command must be issued and a delay of tRCD incurred.

Figure 7. ACTV Command

ACTV

DDR_CLK
DDR_CLK
DDR_CKE
DDR_CS
DDR_RAS
DDR_CAS
DDR_WE
DDR_A[12:0]	ROW

DDR_BA[2:0] BANK

DDR_DQM[3:0]

DDR2 Memory Controller

SPRUEM4A–November 2007

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Texas Instruments TMS320C642x DSP manual Activation ACTV, ACTV Command, DDRA120

Contents

Users Guide TMS320C642x DSP DDR2 Memory ControllerSPRUEM4A-November Submit Documentation FeedbackContents List of Figures List of FiguresList of Tables Read This First PrefaceAbout This Manual Notational ConventionsDDR2 Memory Controller Users Guide1.2 Features 1 Introduction1.3 Functional Block Diagram 1.4 Supported Use Case Statement1.5 Industry Standards Compliance Statement Figure 1. Data Paths to DDR2 Memory ControllerFigure 2. DDR2 Memory Controller Clock Block Diagram 2 Peripheral Architecture2.1 Clock Control 2.1.1 Clock Source2.1.2 Clock Configuration Table 1. PLLC2 Configuration2.2 Memory Map 2.1.3 DDR2 Memory Controller Internal Clock Domains2.3 Signal Descriptions Figure 3. DDR2 Memory Controller SignalsTable 2. DDR2 Memory Controller Signal Descriptions Peripheral ArchitectureTable 3. DDR2 SDRAM Commands Table 4. Truth Table for DDR2 SDRAM Commands2.4 Protocol Descriptions Peripheral ArchitectureFigure 4. Refresh Command 2.4.1 Refresh ModeDDRCLK DDRCLK DDRCKE DDRCS DDRRAS DDRCAS DDRWE DDRA120 DDRBA20 DDRDQM30Figure 5. DCAB Command 2.4.2 Deactivation DCAB and DEACDCAB DDRCLK DDRCLK DDRCKE DDRCS DDRRAS DDRCAS DDRWE DDRA12,11 DDRA10 DDRBA20 DDRDQM30Figure 6. DEAC Command Peripheral ArchitectureDDR2 Memory Controller Submit Documentation Feedback2.4.3 Activation ACTV Figure 7. ACTV CommandDDRA120 2.4.4 READ Command Figure 8. DDR2 READ CommandDDRCLK DDRCLK DDRCKE DDRCS DDRRAS DDRCAS DDRWE DDRA120 COL DDRBA20 BANK DDRA10 DDRDQM30 CAS Latency2.4.5 Write WRT Command Figure 9. DDR2 WRT CommandFigure 10. DDR2 MRS and EMRS Command 2.4.6 Mode Register Set MRS and EMRSTable 5. Addressable Memory Ranges 2.5 Memory Width and Byte AlignmentFigure 11. Byte Alignment Little-Endian Mode Table 6. 16-Bit External Memory 2.6 Endianness SupportTable 7. 32-Bit External Memory Table 8. Bank Configuration Register Fields for Address Mapping 2.7 Address MappingTable 9. Logical Address-to-DDR2 SDRAM Address Map for 32-Bit SDRAM Table 10. Logical Address-to-DDR2 SDRAM Address Map for 16-bit SDRAMPeripheral Architecture DDR2 Memory ControllerFigure 12. Logical Address-to-DDR2 SDRAM Address Map Peripheral ArchitectureFigure 13. DDR2 SDRAM Column, Row, and Bank Access Peripheral ArchitectureDDR2 Memory Controller Submit Documentation Feedback2.8 DDR2 Memory Controller Interface Figure 14. DDR2 Memory Controller FIFO Block DiagramTable 11. DDR2 Memory Controller FIFO Description 2.8.1 Command Ordering and Scheduling, Advanced Concept 2.8.2 Command Starvation 2.8.3 Possible Race Condition2.10 Self-Refresh Mode 2.9 Refresh SchedulingTable 12. Refresh Urgency Levels Table 13. Reset Sources 2.11 Reset ConsiderationsFigure 15. DDR2 Memory Controller Reset Block Diagram 2.12 VTP IO Buffer Calibration 2.13 Auto-Initialization SequenceTable 14. DDR2 SDRAM Configuration by MRS Command Table 15. DDR2 SDRAM Configuration by EMRS1 Command2.13.1 Initializing Configuration Registers Write recovery from autoprecharge. Value of2.13.2 Initializing Following Device Power Up and Device RESET 2.16 Power Management Figure 16. DDR2 Memory Controller Power Sleep Controller Diagram2.14 Interrupt Support 2.15 DMA Event Support2.16.1 DDR2 Memory Controller Clock Stop Procedure 2.17 Emulation Considerations3.1 Connecting the DDR2 Memory Controller to DDR2 Memory 3 Supported Use CasesFigure 17. Connecting DDR2 Memory Controller for 32-Bit Connection Figure 18. Connecting DDR2 Memory Controller for 16-Bit ConnectionSupported Use Cases 200 Ω 200 Ω3.2.1 Configuring SDRAM Bank Configuration Register SDBCR Table 16. SDRAM Bank Configuration Register SDBCR Configuration3.2.2 Configuring SDRAM Refresh Control Register SDRCR Table 17. DDR2 Memory Refresh SpecificationTable 19. SDRAM Timing Register SDTIMR Configuration 3.2.3 Configuring SDRAM Timing Registers SDTIMR and SDTIMR2Table 20. SDRAM Timing Register 2 SDTIMR2 Configuration 3.2.4 Configuring DDR PHY Control Register DDRPHYCR Table 21. DDR PHY Control Register DDRPHYCR Configuration4 DDR2 Memory Controller Registers DDR2 Memory Controller Registers4.1 SDRAM Status Register SDRSTAT Figure 19. SDRAM Status Register SDRSTATTable 25. SDRAM Status Register SDRSTAT Field Descriptions DDR2 Memory Controller Registers4.2 SDRAM Bank Configuration Register SDBCR Figure 20. SDRAM Bank Configuration Register SDBCRTable 26. SDRAM Bank Configuration Register SDBCR Field Descriptions DDR2 Memory Controller RegistersDDR2 Memory Controller Registers DDR2 Memory Controller4.3 SDRAM Refresh Control Register SDRCR Figure 21. SDRAM Refresh Control Register SDRCRTable 27. SDRAM Refresh Control Register SDRCR Field Descriptions DDR2 Memory Controller Registers4.4 SDRAM Timing Register SDTIMR Figure 22. SDRAM Timing Register SDTIMRTable 28. SDRAM Timing Register SDTIMR Field Descriptions DDR2 Memory Controller Registers4.5 SDRAM Timing Register 2 SDTIMR2 Figure 23. SDRAM Timing Register 2 SDTIMR2Table 29. SDRAM Timing Register 2 SDTIMR2 Field Descriptions DDR2 Memory Controller Registers4.6 Peripheral Bus Burst Priority Register PBBPR Figure 24. Peripheral Bus Burst Priority Register PBBPR4.7 Interrupt Raw Register IRR Figure 25. Interrupt Raw Register IRRTable 31. Interrupt Raw Register IRR Field Descriptions DDR2 Memory Controller RegistersFigure 26. Interrupt Masked Register IMR 4.8 Interrupt Masked Register IMRTable 32. Interrupt Masked Register IMR Field Descriptions 4.9 Interrupt Mask Set Register IMSR Figure 27. Interrupt Mask Set Register IMSRTable 33. Interrupt Mask Set Register IMSR Field Descriptions DDR2 Memory Controller Registers4.10 Interrupt Mask Clear Register IMCR Figure 28. Interrupt Mask Clear Register IMCRTable 34. Interrupt Mask Clear Register IMCR Field Descriptions DDR2 Memory Controller Registers4.11 DDR PHY Control Register DDRPHYCR Figure 29. DDR PHY Control Register DDRPHYCRTable 35. DDR PHY Control Register DDRPHYCR Field Descriptions DDR2 Memory Controller Registers4.12 VTP IO Control Register VTPIOCR Figure 30. VTP IO Control Register VTPIOCRTable 36. VTP IO Control Register VTPIOCR Field Descriptions DDR2 Memory Controller Registers4.14 DDR VTP Enable Register DDRVTPER Figure 32. DDR VTP Enable Register DDRVTPERTable 38. DDR VTP Enable Register DDRVTPER Field Descriptions 4.13 DDR VTP Register DDRVTPRAppendix A Revision History Table A-1. Document Revision HistoryAppendix A Sectionpower.ti.com IMPORTANT NOTICEProducts Applications

2.4.3Activation (ACTV)

Figure 7. ACTV Command

DDR_A[12:0]