Manuals / Texas Instruments / Computer Equipment / Network Router

Texas Instruments TMS320C642x DSP manual Endianness Support, 16-Bit External Memory

Models: TMS320C642x DSP

1 57

Download 57 pages 6.18 Kb

Page 21

2.6Endianness Support

www.ti.com

Peripheral Architecture

2.6Endianness Support

The DDR2 memory controller supports both big-endian and little-endian operating modes. The endianness mode selection at the time of an access determines the order in which data on the internal data bus is written to or read from devices that are not as wide as the internal data bus. However, the DDR2 memory controller maintains the natural order of endian operations. That is, a stream of data starting at any address N within any endian environment will always be accessed in the correct or incrementing data order. The DDR2 memory controller will always access address N prior to N + 1 in all endian modes and in any data width. Table 6 and Table 7 show operation of the DDR2 memory controller for both 16-bit and 32-bit external memory in both big-endian and little-endian modes. See the device-specific data manual for the memory widths that are supported.

Since the endianness mode must be determined prior to bootloading, the endian mode selection is latched in the Boot Configuration (BOOTCFG) register when the device is reset. This endianness mode selection is also reflected in the BE bit in the SDRAM status register (SDRSTAT).

Table 6. 16-Bit External Memory

	Big-Endian Mode		Little-Endian Mode
Internal Data (64-Bit)	DDR_A[2:1]	DDR_D[15:0]	DDR_A[2:1]	DDR_D[15:0]
0123 4567 89AB CDEFh	00	0123h	00	CDEFh
0123 4567 89AB CDEFh	01	4567h	01	89ABh
0123 4567 89AB CDEFh	10	89ABh	10	4567h
0123 4567 89AB CDEFh	11	CDEFh	11	0123h

Table 7. 32-Bit External Memory

	Big-Endian Mode		Little-Endian Mode
Internal Data (64-Bit)	DDR_A[2]	DDR_D[31:0]	DDR_A[2]	DDR_D[31:0]
0123 4567 89AB CDEFh	0	89AB CDEFh	0	89AB CDEFh
0123 4567 89AB CDEFh	1	0123 4567h	1	0123 4567h

SPRUEM4A–November 2007	DDR2 Memory Controller	21
Submit Documentation Feedback

Image 21

Texas Instruments TMS320C642x DSP manual Endianness Support, 16-Bit External Memory, 32-Bit External Memory

Contents

TMS320C642x DSP DDR2 Memory Controller Users GuideSubmit Documentation Feedback SPRUEM4A-NovemberContents List of Figures List of FiguresList of Tables Preface Read This FirstAbout This Manual Notational ConventionsUsers Guide DDR2 Memory Controller1.2 Features 1 Introduction1.4 Supported Use Case Statement 1.3 Functional Block Diagram1.5 Industry Standards Compliance Statement Figure 1. Data Paths to DDR2 Memory Controller2 Peripheral Architecture Figure 2. DDR2 Memory Controller Clock Block Diagram2.1 Clock Control 2.1.1 Clock SourceTable 1. PLLC2 Configuration 2.1.2 Clock Configuration2.2 Memory Map 2.1.3 DDR2 Memory Controller Internal Clock DomainsFigure 3. DDR2 Memory Controller Signals 2.3 Signal DescriptionsTable 2. DDR2 Memory Controller Signal Descriptions Peripheral ArchitectureTable 4. Truth Table for DDR2 SDRAM Commands Table 3. DDR2 SDRAM Commands2.4 Protocol Descriptions Peripheral Architecture2.4.1 Refresh Mode Figure 4. Refresh CommandDDRCLK DDRCLK DDRCKE DDRCS DDRRAS DDRCAS DDRWE DDRA120 DDRBA20 DDRDQM302.4.2 Deactivation DCAB and DEAC Figure 5. DCAB CommandDCAB DDRCLK DDRCLK DDRCKE DDRCS DDRRAS DDRCAS DDRWE DDRA12,11 DDRA10 DDRBA20 DDRDQM30Peripheral Architecture Figure 6. DEAC CommandDDR2 Memory Controller Submit Documentation FeedbackFigure 7. ACTV Command 2.4.3 Activation ACTVDDRA120 Figure 8. DDR2 READ Command 2.4.4 READ CommandDDRCLK DDRCLK DDRCKE DDRCS DDRRAS DDRCAS DDRWE DDRA120 COL DDRBA20 BANK DDRA10 DDRDQM30 CAS LatencyFigure 9. DDR2 WRT Command 2.4.5 Write WRT Command2.4.6 Mode Register Set MRS and EMRS Figure 10. DDR2 MRS and EMRS Command2.5 Memory Width and Byte Alignment Table 5. Addressable Memory RangesFigure 11. Byte Alignment Little-Endian Mode 2.6 Endianness Support Table 6. 16-Bit External MemoryTable 7. 32-Bit External Memory 2.7 Address Mapping Table 8. Bank Configuration Register Fields for Address MappingTable 10. Logical Address-to-DDR2 SDRAM Address Map for 16-bit SDRAM Table 9. Logical Address-to-DDR2 SDRAM Address Map for 32-Bit SDRAMPeripheral Architecture DDR2 Memory ControllerPeripheral Architecture Figure 12. Logical Address-to-DDR2 SDRAM Address MapPeripheral Architecture Figure 13. DDR2 SDRAM Column, Row, and Bank AccessDDR2 Memory Controller Submit Documentation FeedbackFigure 14. DDR2 Memory Controller FIFO Block Diagram 2.8 DDR2 Memory Controller InterfaceTable 11. DDR2 Memory Controller FIFO Description 2.8.1 Command Ordering and Scheduling, Advanced Concept 2.8.3 Possible Race Condition 2.8.2 Command Starvation2.9 Refresh Scheduling 2.10 Self-Refresh ModeTable 12. Refresh Urgency Levels 2.11 Reset Considerations Table 13. Reset SourcesFigure 15. DDR2 Memory Controller Reset Block Diagram 2.13 Auto-Initialization Sequence 2.12 VTP IO Buffer CalibrationTable 15. DDR2 SDRAM Configuration by EMRS1 Command Table 14. DDR2 SDRAM Configuration by MRS Command2.13.1 Initializing Configuration Registers Write recovery from autoprecharge. Value of2.13.2 Initializing Following Device Power Up and Device RESET Figure 16. DDR2 Memory Controller Power Sleep Controller Diagram 2.16 Power Management2.14 Interrupt Support 2.15 DMA Event Support2.17 Emulation Considerations 2.16.1 DDR2 Memory Controller Clock Stop Procedure3 Supported Use Cases 3.1 Connecting the DDR2 Memory Controller to DDR2 MemoryFigure 18. Connecting DDR2 Memory Controller for 16-Bit Connection Figure 17. Connecting DDR2 Memory Controller for 32-Bit ConnectionSupported Use Cases 200 Ω 200 ΩTable 16. SDRAM Bank Configuration Register SDBCR Configuration 3.2.1 Configuring SDRAM Bank Configuration Register SDBCR3.2.2 Configuring SDRAM Refresh Control Register SDRCR Table 17. DDR2 Memory Refresh Specification3.2.3 Configuring SDRAM Timing Registers SDTIMR and SDTIMR2 Table 19. SDRAM Timing Register SDTIMR ConfigurationTable 20. SDRAM Timing Register 2 SDTIMR2 Configuration Table 21. DDR PHY Control Register DDRPHYCR Configuration 3.2.4 Configuring DDR PHY Control Register DDRPHYCRDDR2 Memory Controller Registers 4 DDR2 Memory Controller RegistersFigure 19. SDRAM Status Register SDRSTAT 4.1 SDRAM Status Register SDRSTATTable 25. SDRAM Status Register SDRSTAT Field Descriptions DDR2 Memory Controller RegistersFigure 20. SDRAM Bank Configuration Register SDBCR 4.2 SDRAM Bank Configuration Register SDBCRTable 26. SDRAM Bank Configuration Register SDBCR Field Descriptions DDR2 Memory Controller RegistersDDR2 Memory Controller DDR2 Memory Controller RegistersFigure 21. SDRAM Refresh Control Register SDRCR 4.3 SDRAM Refresh Control Register SDRCRTable 27. SDRAM Refresh Control Register SDRCR Field Descriptions DDR2 Memory Controller RegistersFigure 22. SDRAM Timing Register SDTIMR 4.4 SDRAM Timing Register SDTIMRTable 28. SDRAM Timing Register SDTIMR Field Descriptions DDR2 Memory Controller RegistersFigure 23. SDRAM Timing Register 2 SDTIMR2 4.5 SDRAM Timing Register 2 SDTIMR2Table 29. SDRAM Timing Register 2 SDTIMR2 Field Descriptions DDR2 Memory Controller RegistersFigure 24. Peripheral Bus Burst Priority Register PBBPR 4.6 Peripheral Bus Burst Priority Register PBBPRFigure 25. Interrupt Raw Register IRR 4.7 Interrupt Raw Register IRRTable 31. Interrupt Raw Register IRR Field Descriptions DDR2 Memory Controller Registers4.8 Interrupt Masked Register IMR Figure 26. Interrupt Masked Register IMRTable 32. Interrupt Masked Register IMR Field Descriptions Figure 27. Interrupt Mask Set Register IMSR 4.9 Interrupt Mask Set Register IMSRTable 33. Interrupt Mask Set Register IMSR Field Descriptions DDR2 Memory Controller RegistersFigure 28. Interrupt Mask Clear Register IMCR 4.10 Interrupt Mask Clear Register IMCRTable 34. Interrupt Mask Clear Register IMCR Field Descriptions DDR2 Memory Controller RegistersFigure 29. DDR PHY Control Register DDRPHYCR 4.11 DDR PHY Control Register DDRPHYCRTable 35. DDR PHY Control Register DDRPHYCR Field Descriptions DDR2 Memory Controller RegistersFigure 30. VTP IO Control Register VTPIOCR 4.12 VTP IO Control Register VTPIOCRTable 36. VTP IO Control Register VTPIOCR Field Descriptions DDR2 Memory Controller RegistersFigure 32. DDR VTP Enable Register DDRVTPER 4.14 DDR VTP Enable Register DDRVTPERTable 38. DDR VTP Enable Register DDRVTPER Field Descriptions 4.13 DDR VTP Register DDRVTPRTable A-1. Document Revision History Appendix A Revision HistoryAppendix A SectionIMPORTANT NOTICE power.ti.comProducts Applications