Protocol Descriptions | Texas Instruments TMS320C642x DSP specification

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Peripheral Architecture

2.4Protocol Description(s)

The DDR2 memory controller supports the DDR2 SDRAM commands listed in Table 3. Table 4 shows the signal truth table for the DDR2 SDRAM commands.

	Table 3. DDR2 SDRAM Commands
Command	Function
ACTV	Activates the selected bank and row.
DCAB	Precharge all command. Deactivates (precharges) all banks.
DEAC	Precharge single command. Deactivates (precharges) a single bank.
DESEL	Device Deselect.
EMRS	Extended Mode Register set. Allows altering the contents of the mode register.
MRS	Mode register set. Allows altering the contents of the mode register.
NOP	No operation.
Power Down	Power down mode.
READ	Inputs the starting column address and begins the read operation.
READ with	Inputs the starting column address and begins the read operation. The read operation is followed by a
autoprecharge	precharge.
REFR	Autorefresh cycle.
SLFREFR	Self-refresh mode.
WRT	Inputs the starting column address and begins the write operation.
WRT with	Inputs the starting column address and begins the write operation. The write operation is followed by a
autoprecharge	precharge.

Table 4. Truth Table for DDR2 SDRAM Commands

DDR2
SDRAM:	CKE		CS	RAS	CAS	WE	BA[2:0]	A[12:11, 9:0]	A10
DDR2
memory
controller:		DDR_CKE	DDR_CS	DDR_RAS	DDR_CAS	DDR_WE	DDR_BA[2:0]	DDR_A[12:11, 9:0]	DDR_A[10]
	Previous
	Cycles	Current Cycle
ACTV	H	H	L	L	H	H	Bank	Row Address
DCAB	H	H	L	L	H	L	X	X	L
DEAC	H	H	L	L	H	L	Bank	X	L
MRS	H	H	L	L	L	L	BA	OP Code
EMRS	H	H	L	L	L	L	BA	OP Code
READ	H	H	L	H	L	H	BA	Column Address	L
READ with	H	H	L	H	L	H	BA	Column Address	H
precharge
WRT	H	H	L	H	L	L	BA	Column Address	L
WRT with	H	H	L	H	L	L	BA	Column Address	L
precharge
REFR	H	H	L	L	L	H	X	X	X
SLFREFR	H	L	L	L	L	H	X	X	X
entry
SLFREFR	L	H	H	X	X	X	X	X	X
exit			L	H	H	H	X	X	X
			L	H	H	H	X	X	X
NOP	H	X	L	H	H	H	X	X	X
DESEL	H	X	H	X	X	X	X	X	X
Power Down	H	L	H	X	X	X	X	X	X
entry			L	H	H	H	X	X	X
			L	H	H	H	X	X	X
Power Down	L	H	H	X	X	X	X	X	X
exit			L	H	H	H	X	X	X
			L	H	H	H	X	X	X

12

DDR2 Memory Controller

SPRUEM4A–November 2007

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Texas Instruments TMS320C642x DSP manual Protocol Descriptions, Truth Table for DDR2 Sdram Commands, Command Function

Contents

Users Guide Submit Documentation Feedback Contents List of Figures List of Tables Read This First Features Purpose of the Peripheral Functional Block Diagram Supported Use Case StatementIndustry Standards Compliance Statement Clock Control Clock Source Clock Configuration PLLC2 ConfigurationMemory Map 3 DDR2 Memory Controller Internal Clock Domains Signal Descriptions DDR2 Memory Controller Signal DescriptionsClock enable Active high Pin Type Description DDR2 Sdram Commands Truth Table for DDR2 Sdram CommandsCommand Function Protocol Descriptions Refresh Mode Refresh Command Dcab Command Deactivation Dcab and Deac Deac Command Actv Command Activation Actv Read Command DDR2 Read Command Write WRT Command DDR2 WRT Command Mode Register Set MRS and Emrs DDR2 MRS and Emrs Command Memory Width and Byte Alignment Addressable Memory Ranges Endianness Support Bit External Memory Bank Configuration Register Fields for Address Mapping Address MappingBit Field Bit Value Bit Description Logical Address-to-DDR2 Sdram Address Map for 32-Bit Sdram Logical Address-to-DDR2 Sdram Address Map for 16-bit Sdram Logical Address-to-DDR2 Sdram Address Map DDR2 Sdram Column, Row, and Bank Access DDR2 Memory Controller Interface DDR2 Memory Controller Fifo Description Command Ordering and Scheduling, Advanced Concept Command Starvation Possible Race Condition Self-Refresh Mode Refresh SchedulingRefresh Urgency Levels Urgency Level Description Reset Considerations Reset SourcesReset Signal Reset Source VTP IO Buffer Calibration Auto-Initialization Sequence DDR2 Sdram Configuration by MRS Command DDR2 Sdram Configuration by EMRS1 CommandInitializing Configuration Registers DDR2 Memory Controller Peripheral Architecture Power Management Interrupt SupportDMA Event Support Emulation Considerations Connecting the DDR2 Memory Controller to DDR2 Memory Supported Use Cases Connecting DDR2 Memory Controller for 32-Bit Connection Configuring Sdram Bank Configuration Register Sdbcr Sdram Bank Configuration Register Sdbcr ConfigurationConfiguring Sdram Refresh Control Register Sdrcr DDR2 Memory Refresh Specification Configuring Sdram Timing Registers Sdtimr and SDTIMR2 Sdram Timing Register Sdtimr ConfigurationSdram Timing Register 2 SDTIMR2 Configuration DDR2 Data Register Field Manual Data Manual Formula Configuring DDR PHY Control Register Ddrphycr DDR PHY Control Register Ddrphycr ConfigurationRegister Field Name Description Mode D63-32 D31-0Acronym Register Description DDR VTP Register Sdram Status Register Sdrstat Sdram Status Register Sdrstat Field DescriptionsBit Field Sdram Bank Configuration Register Sdbcr Sdram Bank Configuration Register Sdbcr Field DescriptionsBit Field Value Description Reserved Reserved. Always write a 0 to this bit Sdram Refresh Control Register Sdrcr Sdram Refresh Control Register Sdrcr Field Descriptions Sdram Timing Register Sdtimr Sdram Timing Register Sdtimr Field Descriptions Sdram Timing Register 2 SDTIMR2 Sdram Timing Register 2 SDTIMR2 Field Descriptions Peripheral Bus Burst Priority Register Pbbpr Peripheral Bus Burst Priority Register Pbbpr Interrupt Raw Register IRR Interrupt Raw Register IRR Field Descriptions Interrupt Masked Register IMR Interrupt Masked Register IMR Field Descriptions Interrupt Mask Set Register Imsr Interrupt Mask Set Register Imsr Field Descriptions Interrupt Mask Clear Register Imcr Interrupt Mask Clear Register Imcr Field Descriptions DDR PHY Control Register Ddrphycr DDR PHY Control Register Ddrphycr Field Descriptions VTP IO Control Register Vtpiocr VTP IO Control Register Vtpiocr Field Descriptions DDR VTP Enable Register Ddrvtper DDR VTP Enable Register Ddrvtper Field DescriptionsDDR VTP Register Ddrvtpr DDR VTP Register Ddrvtpr Field Descriptions Table A-1. Document Revision History Additions/Modifications/Deletions Important Notice