VTP IO Control Register Vtpiocr | Texas Instruments TMS320C642x DSP

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DDR2 Memory Controller Registers

4.12 VTP IO Control Register (VTPIOCR)

The VTP IO control register (VTPIOCR) is used to control the calibration of the DDR2 memory controller IOs with respect to voltage, temperature, and process (VTP). The voltage, temperature, and process information is used to control the IO's output impedance. The VTPIOCR is shown in Figure 30 and described in Table 36.

Figure 30. VTP IO Control Register (VTPIOCR)

31									16
						Reserved
						R-0
15	14	13	12	11	10	9	5	4	0
RECAL	Rsvd	EN	Reserved		Rsvd	PCH			NCH
R/W-0	R/W-0	R/W-0	R/W-0		R-0	R/W-0			R/W-1Fh

LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

Table 36. VTP IO Control Register (VTPIOCR) Field Descriptions

Bit	Field	Value	Description
31-16	Reserved	0	Reserved
15	RECAL		Start VTP IO calibration.
		0	Normal operation
		1	Transition from 0 to 1 starts VTP IO calibration.
14	Reserved	0	Reserved. Always write a 0 to this bit.
13	EN		VTP enable.
		0	VTP IO calibration is disabled.
		1	VTP IO calibration is enabled.
12-11	Reserved	0	Reserved. Always write a 0 to this bit.
10	Reserved	0	Reserved
9-5	PCH	0-1Fh	P channel value. This value is driven to the IO to calibrate the impedance of the IO. The value of PCH
			is determined by reading the DDR VTP register (DDRVTPR). See Section 4.13 for details.
4-0	NCH	0-1Fh	N channel value. This value is driven to the IO to calibrate the impedance of the IO. The value of NCH
			is determined by reading the DDR VTP register (DDRVTPR). See Section 4.13 for details.

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DDR2 Memory Controller

SPRUEM4A–November 2007

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Texas Instruments TMS320C642x DSP manual VTP IO Control Register Vtpiocr Field Descriptions

Contents

Users Guide Submit Documentation Feedback Contents List of Figures List of Tables Read This First Features Purpose of the Peripheral Functional Block Diagram Supported Use Case StatementIndustry Standards Compliance Statement Clock Control Clock Source Memory Map Clock ConfigurationPLLC2 Configuration 3 DDR2 Memory Controller Internal Clock Domains Clock enable Active high Signal DescriptionsDDR2 Memory Controller Signal Descriptions Pin Type Description Command Function DDR2 Sdram CommandsTruth Table for DDR2 Sdram Commands Protocol Descriptions Refresh Mode Refresh Command Dcab Command Deactivation Dcab and Deac Deac Command Actv Command Activation Actv Read Command DDR2 Read Command Write WRT Command DDR2 WRT Command Mode Register Set MRS and Emrs DDR2 MRS and Emrs Command Memory Width and Byte Alignment Addressable Memory Ranges Endianness Support Bit External Memory Bank Configuration Register Fields for Address Mapping Address MappingBit Field Bit Value Bit Description Logical Address-to-DDR2 Sdram Address Map for 32-Bit Sdram Logical Address-to-DDR2 Sdram Address Map for 16-bit Sdram Logical Address-to-DDR2 Sdram Address Map DDR2 Sdram Column, Row, and Bank Access DDR2 Memory Controller Interface DDR2 Memory Controller Fifo Description Command Ordering and Scheduling, Advanced Concept Command Starvation Possible Race Condition Refresh Urgency Levels Self-Refresh ModeRefresh Scheduling Urgency Level Description Reset Considerations Reset SourcesReset Signal Reset Source VTP IO Buffer Calibration Auto-Initialization Sequence Initializing Configuration Registers DDR2 Sdram Configuration by MRS CommandDDR2 Sdram Configuration by EMRS1 Command DDR2 Memory Controller Peripheral Architecture Power Management Interrupt SupportDMA Event Support Emulation Considerations Connecting the DDR2 Memory Controller to DDR2 Memory Supported Use Cases Connecting DDR2 Memory Controller for 32-Bit Connection Configuring Sdram Refresh Control Register Sdrcr Configuring Sdram Bank Configuration Register SdbcrSdram Bank Configuration Register Sdbcr Configuration DDR2 Memory Refresh Specification Sdram Timing Register 2 SDTIMR2 Configuration Configuring Sdram Timing Registers Sdtimr and SDTIMR2Sdram Timing Register Sdtimr Configuration DDR2 Data Register Field Manual Data Manual Formula Configuring DDR PHY Control Register Ddrphycr DDR PHY Control Register Ddrphycr ConfigurationRegister Field Name Description Acronym Register Description Mode D63-32D31-0 DDR VTP Register Sdram Status Register Sdrstat Sdram Status Register Sdrstat Field DescriptionsBit Field Sdram Bank Configuration Register Sdbcr Sdram Bank Configuration Register Sdbcr Field DescriptionsBit Field Value Description Reserved Reserved. Always write a 0 to this bit Sdram Refresh Control Register Sdrcr Sdram Refresh Control Register Sdrcr Field Descriptions Sdram Timing Register Sdtimr Sdram Timing Register Sdtimr Field Descriptions Sdram Timing Register 2 SDTIMR2 Sdram Timing Register 2 SDTIMR2 Field Descriptions Peripheral Bus Burst Priority Register Pbbpr Peripheral Bus Burst Priority Register Pbbpr Interrupt Raw Register IRR Interrupt Raw Register IRR Field Descriptions Interrupt Masked Register IMR Interrupt Masked Register IMR Field Descriptions Interrupt Mask Set Register Imsr Interrupt Mask Set Register Imsr Field Descriptions Interrupt Mask Clear Register Imcr Interrupt Mask Clear Register Imcr Field Descriptions DDR PHY Control Register Ddrphycr DDR PHY Control Register Ddrphycr Field Descriptions VTP IO Control Register Vtpiocr VTP IO Control Register Vtpiocr Field Descriptions DDR VTP Register Ddrvtpr DDR VTP Enable Register DdrvtperDDR VTP Enable Register Ddrvtper Field Descriptions DDR VTP Register Ddrvtpr Field Descriptions Table A-1. Document Revision History Additions/Modifications/Deletions Important Notice