Texas Instruments TMS320C642x DSP manual Emulation Considerations

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Peripheral Architecture

2.16.1DDR2 Memory Controller Clock Stop Procedure

CAUTION

The following clock stop procedures are preliminary and are documented to reflect the intended-use cases. These clock stop procedures may change at a future date.

Note: If an access occurs to the DDR2 memory controller after completing steps 1-5, the DLL will wake up and lock, then the MCLK will turn on and the access will be performed. Following step 6, all DDR2 accesses are disabled until the DDR2 memory controller is enabled again through the LPSC.

To achieve maximum power savings VCLK, MCLK, X2_CLK, DDR_CLK, and DDR_CLK should be gated off, as well as the DDR2 memory controller DLL powered down. Perform the following procedure when shutting down clocks to achieve maximum power savings:

1.Allow software to complete the desired DDR2 transfers.

2.Set the SR bit in the DDR2 SDRAM refresh control register (SDRCR). The DDR2 memory controller will complete any outstanding accesses and backlogged refresh cycles and then place the external DDR2 memory in self-refresh mode.

3.Set the MCLKSTOPEN bit in SDRCR. This enables the DDR2 memory controller to shut off the MCLK.

4.Set the DLLPWRDN bit in the DDR PHY control register (DDRPHYCR) to 1 to power down the DDR2 memory controller DLL.

5.Poll the PHYRDY bit in the SDRAM status register (SDRSTAT) to be a logic-low indicating that the MCLK has been stopped and the DLL is powered down.

6.Program DDR2 memory controller LPSC to disable VCLK.

7.Program PLLC2 registers to stop PLL2_SYSCLK1 which disables X2_CLK of the DDR2 memory controller, as well as DDR_CLK and DDR_CLK.

To turn clocks back on:

1.Program PLLC2 registers to start PLL2_SYSCLK1 which sources X2_CLK of the DDR2 memory controller.

2.Once PLL2_SYSCLK1 is stable, program the DDR2 memory controller LPSC to enable VCLK.

3.Clear the MCLKSTOPEN bit in the DDR2 SDRAM refresh control register (SDRCR) to 0.

4.Clear the DLLPWRDN bit in the DDR PHY control register (DDRPHYCR) to 0 to power up the DDR2 memory controller DLL.

5.Perform a soft reset of the DDR2 memory controller via the PSC using the following procedure. See the TMS320C642x DSP Power and Sleep Controller (PSC) User's Guide (SPRUEN8) for details on how to program the PSC.

a.To put the DDR2 memory controller into soft reset, program the PSC to place the DDR2 memory controller into the SyncReset state.

b.To take the DDR2 memory controller out of soft reset, program the PSC to place the DDR2 memory controller into the Enable state.

6.Clear the SR bit in SDRCR to 0.

2.17Emulation Considerations

The DDR2 memory controller will remain fully functional during emulation halts to allow emulation access to external memory.

SPRUEM4A–November 2007 DDR2 Memory Controller 35

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