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DDR2 Memory Controller Registers
4.6Peripheral Bus Burst Priority Register (PBBPR)
The peripheral bus burst priority register (PBBPR) helps prevent command starvation within the DDR2 memory controller. To avoid command starvation, the DDR2 memory controller momentarily raises the priority of the oldest command in the command FIFO after a set number of transfers have been made. The PR_OLD_COUNT bit sets the number of transfers that must be made before the DDR2 memory controller raises the priority of the oldest command. The PBBPR is shown in Figure 24 and described in Table 30. See Section 2.8.2 for more details on command starvation.
Figure 24. Peripheral Bus Burst Priority Register (PBBPR)
31 |
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| 16 |
| Reserved |
| |
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15 | 8 | 7 | 0 |
Reserved |
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| PR_OLD_COUNT |
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LEGEND: R/W = Read/Write; R = Read only;
Table 30. Peripheral Bus Burst Priority Register (PBBPR) Field Descriptions
Bit | Field | Value | Description |
Reserved | 0 | Reserved | |
PR_OLD_COUNT | Priority raise old counter. Specifies the number of memory transfers after which the DDR2 | ||
|
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| memory controller will elevate the priority of the oldest command in the command FIFO. Setting |
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| this field to FFh disables this feature, thereby allowing old commands to stay in the FIFO |
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| indefinitely. |
|
| 0 | 1 memory transfer |
|
| 1 | 2 memory transfers |
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| 2 | 3 memory transfers |
|
| 4 to 255 memory transfers | |
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| FFh | Feature disabled, commands may stay in command FIFO indefinitely |
48 | DDR2 Memory Controller |