List of Tables

 

1

PLLC2 Configuration

10

2

DDR2 Memory Controller Signal Descriptions

11

3

DDR2 SDRAM Commands

12

4

Truth Table for DDR2 SDRAM Commands

12

5

Addressable Memory Ranges

20

6

16-Bit External Memory

21

7

32-Bit External Memory

21

8

Bank Configuration Register Fields for Address Mapping

22

9

Logical Address-to-DDR2 SDRAM Address Map for 32-Bit SDRAM

23

10

Logical Address-to-DDR2 SDRAM Address Map for 16-bit SDRAM

23

11

DDR2 Memory Controller FIFO Description

26

12

Refresh Urgency Levels

29

13

Reset Sources

30

14

DDR2 SDRAM Configuration by MRS Command

32

15

DDR2 SDRAM Configuration by EMRS(1) Command

32

16

SDRAM Bank Configuration Register (SDBCR) Configuration

38

17

DDR2 Memory Refresh Specification

38

18

SDRAM Refresh Control Register (SDRCR) Configuration

38

19

SDRAM Timing Register (SDTIMR) Configuration

39

20

SDRAM Timing Register 2 (SDTIMR2) Configuration

39

21

DDR PHY Control Register (DDRPHYCR) Configuration

40

22

DDR2 Memory Controller Registers Relative to Base Address 2000 0000h

41

23

DDR2 Memory Controller Registers Relative to Base Address 01C4 2000h

41

24

DDR2 Memory Controller Registers Relative to Base Address 01C4 0000h

41

25

SDRAM Status Register (SDRSTAT) Field Descriptions

42

26

SDRAM Bank Configuration Register (SDBCR) Field Descriptions

43

27

SDRAM Refresh Control Register (SDRCR) Field Descriptions

45

28

SDRAM Timing Register (SDTIMR) Field Descriptions

46

29

SDRAM Timing Register 2 (SDTIMR2) Field Descriptions

47

30

Peripheral Bus Burst Priority Register (PBBPR) Field Descriptions

48

31

Interrupt Raw Register (IRR) Field Descriptions

49

32

Interrupt Masked Register (IMR) Field Descriptions

50

33

Interrupt Mask Set Register (IMSR) Field Descriptions

51

34

Interrupt Mask Clear Register (IMCR) Field Descriptions

52

35

DDR PHY Control Register (DDRPHYCR) Field Descriptions

53

36

VTP IO Control Register (VTPIOCR) Field Descriptions

54

37

DDR VTP Register (DDRVTPR) Field Descriptions

55

38

DDR VTP Enable Register (DDRVTPER) Field Descriptions

55

A-1

Document Revision History

56

SPRUEM4A–November 2007

List of Tables

5

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Texas Instruments TMS320C642x DSP manual List of Tables