Texas Instruments TMS320C642x DSP manual Mode D63-32, D31-0, Acronym Register Description

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DDR2 Memory Controller Registers

4DDR2 Memory Controller Registers

Table 22 lists the memory-mapped registers related to the DDR2 memory controller. See the device-specific data manual for the memory addresses of these registers.

The DDR2 memory controller peripheral interfaces to the CPU using a 64-bit data bus, and supports both big-endian and little-endian operating modes (see Section 2.6 for more information regarding big-endian and little-endian mode operation).

The DDR2 memory controller memory-mapped registers are 32-bit registers, and when accessing them via the 64-bit interface, 32-bit words are swapped internally depending on the selected endianness so that the register memory-map is the same for both big-endian and little-endian modes. This allows the same code to be run regardless of endianness. This includes code that is bootloaded, or code from other sources. Therefore, for example, when accessing the SDRAM bank configuration register (SDBCR) and the SDRAM refresh control register (SDRCR), the following data is obtained:

Mode	D63-32
Little-Endian	SDRAM refresh control register (SDRCR)
Big-Endian	SDRAM bank configuration register (SDBCR)

D31-0

SDRAM bank configuration register (SDBCR)

SDRAM refresh control register (SDRCR)

Table 22. DDR2 Memory Controller Registers Relative to Base Address 2000 0000h

Offset	Acronym	Register Description	Section
4h	SDRSTAT	SDRAM Status Register	Section 4.1
8h	SDBCR	SDRAM Bank Configuration Register	Section 4.2
Ch	SDRCR	SDRAM Refresh Control Register	Section 4.3
10h	SDTIMR	SDRAM Timing Register	Section 4.4
14h	SDTIMR2	SDRAM Timing Register 2	Section 4.5
20h	PBBPR	Peripheral Bus Burst Priority Register	Section 4.6
C0h	IRR	Interrupt Raw Register	Section 4.7
C4h	IMR	Interrupt Masked Register	Section 4.8
C8h	IMSR	Interrupt Mask Set Register	Section 4.9
CCh	IMCR	Interrupt Mask Clear Register	Section 4.10
E4h	DDRPHYCR	DDR PHY Control Register	Section 4.11
F0h	VTPIOCR	VTP IO Control Register	Section 4.12

Table 23. DDR2 Memory Controller Registers Relative to Base Address 01C4 2000h

Offset	Acronym	Register Description	Section
38h	DDRVTPR	DDR VTP Register	Section 4.13

Table 24. DDR2 Memory Controller Registers Relative to Base Address 01C4 0000h

Offset	Acronym	Register Description	Section
4Ch	DDRVTPER	DDR VTP Enable Register	Section 4.14

SPRUEM4A–November 2007	DDR2 Memory Controller	41
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