List of Figures | Texas Instruments TMS320C642x DSP guide

	List of Figures
1	Data Paths to DDR2 Memory Controller	8
2	DDR2 Memory Controller Clock Block Diagram	9
3	DDR2 Memory Controller Signals	11
4	Refresh Command	13
5	DCAB Command	14
6	DEAC Command	15
7	ACTV Command	16
8	DDR2 READ Command	17
9	DDR2 WRT Command	18
10	DDR2 MRS and EMRS Command	19
11	Byte Alignment (Little-Endian Mode)	20
12	Logical Address-to-DDR2 SDRAM Address Map	24
13	DDR2 SDRAM Column, Row, and Bank Access	25
14	DDR2 Memory Controller FIFO Block Diagram	26
15	DDR2 Memory Controller Reset Block Diagram	30
16	DDR2 Memory Controller Power Sleep Controller Diagram	34
17	Connecting DDR2 Memory Controller for 32-Bit Connection	37
18	Connecting DDR2 Memory Controller for 16-Bit Connection	37
19	SDRAM Status Register (SDRSTAT)	42
20	SDRAM Bank Configuration Register (SDBCR)	43
21	SDRAM Refresh Control Register (SDRCR)	45
22	SDRAM Timing Register (SDTIMR)	46
23	SDRAM Timing Register 2 (SDTIMR2)	47
24	Peripheral Bus Burst Priority Register (PBBPR)	48
25	Interrupt Raw Register (IRR)	49
26	Interrupt Masked Register (IMR)	50
27	Interrupt Mask Set Register (IMSR)	51
28	Interrupt Mask Clear Register (IMCR)	52
29	DDR PHY Control Register (DDRPHYCR)	53
30	VTP IO Control Register (VTPIOCR)	54
31	DDR VTP Register (DDRVTPR)	55
32	DDR VTP Enable Register (DDRVTPER)	55

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List of Figures

SPRUEM4A–November 2007

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Texas Instruments TMS320C642x DSP manual List of Figures

Contents

Users Guide Submit Documentation Feedback Contents List of Figures List of Tables Read This First Features Purpose of the Peripheral Supported Use Case Statement Functional Block DiagramIndustry Standards Compliance Statement Clock Control Clock Source Clock Configuration PLLC2 ConfigurationMemory Map 3 DDR2 Memory Controller Internal Clock Domains Signal Descriptions DDR2 Memory Controller Signal DescriptionsClock enable Active high Pin Type Description DDR2 Sdram Commands Truth Table for DDR2 Sdram CommandsCommand Function Protocol Descriptions Refresh Mode Refresh Command Dcab Command Deactivation Dcab and Deac Deac Command Actv Command Activation Actv Read Command DDR2 Read Command Write WRT Command DDR2 WRT Command Mode Register Set MRS and Emrs DDR2 MRS and Emrs Command Memory Width and Byte Alignment Addressable Memory Ranges Endianness Support Bit External Memory Address Mapping Bank Configuration Register Fields for Address MappingBit Field Bit Value Bit Description Logical Address-to-DDR2 Sdram Address Map for 32-Bit Sdram Logical Address-to-DDR2 Sdram Address Map for 16-bit Sdram Logical Address-to-DDR2 Sdram Address Map DDR2 Sdram Column, Row, and Bank Access DDR2 Memory Controller Interface DDR2 Memory Controller Fifo Description Command Ordering and Scheduling, Advanced Concept Command Starvation Possible Race Condition Self-Refresh Mode Refresh SchedulingRefresh Urgency Levels Urgency Level Description Reset Sources Reset ConsiderationsReset Signal Reset Source VTP IO Buffer Calibration Auto-Initialization Sequence DDR2 Sdram Configuration by MRS Command DDR2 Sdram Configuration by EMRS1 CommandInitializing Configuration Registers DDR2 Memory Controller Peripheral Architecture Interrupt Support Power ManagementDMA Event Support Emulation Considerations Connecting the DDR2 Memory Controller to DDR2 Memory Supported Use Cases Connecting DDR2 Memory Controller for 32-Bit Connection Configuring Sdram Bank Configuration Register Sdbcr Sdram Bank Configuration Register Sdbcr ConfigurationConfiguring Sdram Refresh Control Register Sdrcr DDR2 Memory Refresh Specification Configuring Sdram Timing Registers Sdtimr and SDTIMR2 Sdram Timing Register Sdtimr ConfigurationSdram Timing Register 2 SDTIMR2 Configuration DDR2 Data Register Field Manual Data Manual Formula DDR PHY Control Register Ddrphycr Configuration Configuring DDR PHY Control Register DdrphycrRegister Field Name Description Mode D63-32 D31-0Acronym Register Description DDR VTP Register Sdram Status Register Sdrstat Field Descriptions Sdram Status Register SdrstatBit Field Sdram Bank Configuration Register Sdbcr Field Descriptions Sdram Bank Configuration Register SdbcrBit Field Value Description Reserved Reserved. Always write a 0 to this bit Sdram Refresh Control Register Sdrcr Sdram Refresh Control Register Sdrcr Field Descriptions Sdram Timing Register Sdtimr Sdram Timing Register Sdtimr Field Descriptions Sdram Timing Register 2 SDTIMR2 Sdram Timing Register 2 SDTIMR2 Field Descriptions Peripheral Bus Burst Priority Register Pbbpr Peripheral Bus Burst Priority Register Pbbpr Interrupt Raw Register IRR Interrupt Raw Register IRR Field Descriptions Interrupt Masked Register IMR Interrupt Masked Register IMR Field Descriptions Interrupt Mask Set Register Imsr Interrupt Mask Set Register Imsr Field Descriptions Interrupt Mask Clear Register Imcr Interrupt Mask Clear Register Imcr Field Descriptions DDR PHY Control Register Ddrphycr DDR PHY Control Register Ddrphycr Field Descriptions VTP IO Control Register Vtpiocr VTP IO Control Register Vtpiocr Field Descriptions DDR VTP Enable Register Ddrvtper DDR VTP Enable Register Ddrvtper Field DescriptionsDDR VTP Register Ddrvtpr DDR VTP Register Ddrvtpr Field Descriptions Table A-1. Document Revision History Additions/Modifications/Deletions Important Notice