Texas Instruments TMS320C642x DSP specs

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Peripheral Architecture

Table 9. Logical Address-to-DDR2 SDRAM Address Map for 32-Bit SDRAM

SDBCR Bit										Logical Address(1)
IBANK	PAGESIZE	31	30	29	28	27	26	25	24	23	22:16	15	14	13	12	11	10	9:2	1:0
0	0	-									nrb=13							ncb=8
1	0	-								nrb=13							nbb=1	ncb=8
2h	0	-							nrb=13							nbb=2		ncb=8
3h	0	-						nrb=13							nbb=3			ncb=8
0	1	-								nrb=13							ncb=9
1	1	-							nrb=13							nbb=1	ncb=9
2h	1	-						nrb=13							nbb=2		ncb=9
3h	1	-					nrb=13							nbb=3			ncb=9
0	2h	-							nrb=13							ncb=10
1	2h	-						nrb=13							nbb=1	ncb=10
2h	2h	-					nrb=13							nbb=2		ncb=10
3h	2h	-				nrb=13							nbb=3			ncb=10
0	3h	-						nrb=13							ncb=11
1	3h	-					nrb=13							nbb=1	ncb=11
2h	3h	-				nrb=13							nbb=2		ncb=11
3h	3h				nrb=13							nbb=3			ncb=11

(1)Legend: ncb = number of column address bits; nrb = number of row address bits; nbb = number of bank address bits.

Table 10. Logical Address-to-DDR2 SDRAM Address Map for 16-bit SDRAM

SDBCR Bit										Logical Address(1)
IBANK	PAGESIZE	31	30	29	28	27	26	25	24	23	22	21:15	14	13	12	11	10	9	8:1	0
0	0	-										nrb=13							ncb=8
1	0	-									nrb=13							nbb=1	ncb=8
2h	0	-								nrb=13							nbb=2		ncb=8
3h	0	-							nrb=13							nbb=3			ncb=8
0	1	-									nrb=13							ncb=9
1	1	-								nrb=13							nbb=1	ncb=9
2h	1	-							nrb=13							nbb=2		ncb=9
3h	1	-						nrb=13							nbb=3			ncb=9
0	2h	-								nrb=13							ncb=10
1	2h	-							nrb=13							nbb=1	ncb=10
2h	2h	-						nrb=13							nbb=2		ncb=10
3h	2h	-					nrb=13							nbb=3			ncb=10
0	3h	-							nrb=13							ncb=11
1	3h	-						nrb=13							nbb=1	ncb=11
2h	3h	-					nrb=13							nbb=2		ncb=11
3h	3h	-				nrb=13							nbb=3			ncb=11

(1)Legend: ncb = number of column address bits; nrb = number of row address bits; nbb = number of bank address bits.

SPRUEM4A–November 2007	DDR2 Memory Controller	23
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Texas Instruments TMS320C642x DSP manual Logical Address-to-DDR2 Sdram Address Map for 32-Bit Sdram

Contents

Users Guide Submit Documentation Feedback Contents List of Figures List of Tables Read This First Purpose of the Peripheral Features Industry Standards Compliance Statement Functional Block DiagramSupported Use Case Statement Clock Source Clock Control 3 DDR2 Memory Controller Internal Clock Domains Clock ConfigurationPLLC2 Configuration Memory Map Pin Type Description Signal DescriptionsDDR2 Memory Controller Signal Descriptions Clock enable Active high Protocol Descriptions DDR2 Sdram CommandsTruth Table for DDR2 Sdram Commands Command Function Refresh Command Refresh Mode Deactivation Dcab and Deac Dcab Command Deac Command Activation Actv Actv Command DDR2 Read Command Read Command DDR2 WRT Command Write WRT Command DDR2 MRS and Emrs Command Mode Register Set MRS and Emrs Addressable Memory Ranges Memory Width and Byte Alignment Bit External Memory Endianness Support Bit Field Bit Value Bit Description Bank Configuration Register Fields for Address MappingAddress Mapping Logical Address-to-DDR2 Sdram Address Map for 16-bit Sdram Logical Address-to-DDR2 Sdram Address Map for 32-Bit Sdram Logical Address-to-DDR2 Sdram Address Map DDR2 Sdram Column, Row, and Bank Access DDR2 Memory Controller Fifo Description DDR2 Memory Controller Interface Command Ordering and Scheduling, Advanced Concept Possible Race Condition Command Starvation Urgency Level Description Self-Refresh ModeRefresh Scheduling Refresh Urgency Levels Reset Signal Reset Source Reset ConsiderationsReset Sources Auto-Initialization Sequence VTP IO Buffer Calibration DDR2 Memory Controller DDR2 Sdram Configuration by MRS CommandDDR2 Sdram Configuration by EMRS1 Command Initializing Configuration Registers Peripheral Architecture DMA Event Support Power ManagementInterrupt Support Emulation Considerations Supported Use Cases Connecting the DDR2 Memory Controller to DDR2 Memory Connecting DDR2 Memory Controller for 32-Bit Connection DDR2 Memory Refresh Specification Configuring Sdram Bank Configuration Register SdbcrSdram Bank Configuration Register Sdbcr Configuration Configuring Sdram Refresh Control Register Sdrcr DDR2 Data Register Field Manual Data Manual Formula Configuring Sdram Timing Registers Sdtimr and SDTIMR2Sdram Timing Register Sdtimr Configuration Sdram Timing Register 2 SDTIMR2 Configuration Register Field Name Description Configuring DDR PHY Control Register DdrphycrDDR PHY Control Register Ddrphycr Configuration DDR VTP Register Mode D63-32D31-0 Acronym Register Description Bit Field Sdram Status Register SdrstatSdram Status Register Sdrstat Field Descriptions Bit Field Value Description Sdram Bank Configuration Register SdbcrSdram Bank Configuration Register Sdbcr Field Descriptions Reserved Reserved. Always write a 0 to this bit Sdram Refresh Control Register Sdrcr Field Descriptions Sdram Refresh Control Register Sdrcr Sdram Timing Register Sdtimr Field Descriptions Sdram Timing Register Sdtimr Sdram Timing Register 2 SDTIMR2 Field Descriptions Sdram Timing Register 2 SDTIMR2 Peripheral Bus Burst Priority Register Pbbpr Peripheral Bus Burst Priority Register Pbbpr Interrupt Raw Register IRR Field Descriptions Interrupt Raw Register IRR Interrupt Masked Register IMR Field Descriptions Interrupt Masked Register IMR Interrupt Mask Set Register Imsr Field Descriptions Interrupt Mask Set Register Imsr Interrupt Mask Clear Register Imcr Field Descriptions Interrupt Mask Clear Register Imcr DDR PHY Control Register Ddrphycr Field Descriptions DDR PHY Control Register Ddrphycr VTP IO Control Register Vtpiocr Field Descriptions VTP IO Control Register Vtpiocr DDR VTP Register Ddrvtpr Field Descriptions DDR VTP Enable Register DdrvtperDDR VTP Enable Register Ddrvtper Field Descriptions DDR VTP Register Ddrvtpr Additions/Modifications/Deletions Table A-1. Document Revision History Important Notice